Neural Network Features and SoC Integration for Efficient Computing
Explore the utilization of neural network features in low-power devices for image and speech recognition, with a focus on integrating neural networks into System-on-Chip (SoC) architectures. Discover the challenges and methodologies involved in adapting neural networks to SoCs, including quantization effects and hardware optimization. Validate and analyze these approaches using tools like Matlab, C++, and Xilinx Zynq for prototyping. Join the journey of Vida Abdolzadeh in bridging the gap between neural networks and SoC for enhanced computing capabilities.
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Presentation Transcript
Vida Abdolzadeh Tutor: Prof.Nicola Petra XXXII Cycle - I year presentation Neural network
Background MSc PhD Computer Engineering Tabriz University,Iran Augustus 21th 2014 Electronic Group Prof.Nicola Petra Subject:Computer Architecture Athenaeum fellowship Title: Reversible 4-Bit Parallel Excess-3 Adder For Nanotechnology Based Systems Electronic laboratory Vida Abdolzadeh 2
Why neural network features Layer n Layer 1 Layer 2 classification Features computation Neural networks are widely used today for image and speech recognition: interaction between humans and electronics devices Usually implemented with high-end computers Many applications do not allow the use of high- end PC or the cloud (car devices, smart TV, domotics, IoT, etc.) Vida Abdolzadeh 3
The solution: SoC (System on Chip) Cheap circuits Mid-power architectures that integrates processors and dedicated circuitry on the same chip Adapting neural network to SoCs is not trivial: Quantization effects need to be studied Efficient hardware architecture must be derived Vida Abdolzadeh 4
Methodology Model the effects of circuit approximations on the network reliability (quantization) Derive SoC architectures neural-network ready Derive dedicated neural network co-processors Layer accelerator: Long Short Term Memory Layer Vida Abdolzadeh 5
Validation Numerical analysis: Matlab / C++ Design: High level synthesis and RTL design Prototyping Programmable SoC: Xilinx Zynq Vida Abdolzadeh 6
First year credits Student: Name Surname vida.abdolzadeh@unina.it Tutor: Name Surname nicpetra@unina.it Cycle XXXII Credits year 1 2 3 Credits year 2 2 3 Credits year 3 2 3 1 4 5 6 1 4 5 6 1 4 5 6 Estimated 20 Estimated 10 Estimated Summary 12 Summary Summary bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth Check Total 0 0 1.2 10 8.8 10 0 0 0 0 0 0.8 8 6.2 8 3 9 2 1 Modules Seminars Research 0 0 0 0 0 0 0 0 5.7 10-30 0 39 80-140 0 60 15 30-70 5 4 5 10 10 35 60 44 60 45 60 60 60 10 10 12 0 0 0 0 0 0 0 0 0 0 0 0 180 Vida Abdolzadeh 7
Thank you for your pay attention 8
