One-Hot State Machine Design Fundamentals

ECE 352 Digital System Fundamentals One-Hot State Machine Design One-Hot State Machine Design 1 1

Min FF Example: Ring Counter Could use a minimum flip-flop technique Use an arithmetic order for state assignment A decoder takes in current state and produces the circuit outputs One-Hot State Machine Design reset D FF1 Q DEC 2:4 S0 S1 S2 S3 Y3 Y2 Y1 Y0 1 3 2 1 0 0001 0010 0100 1000 CLRN 0 Output: Y3 Y2 Y1 Y0 D FF0 Q CLK Two flip-flops Four states (00, 01, 10, 11) Reset into state 00 CLRN RST 2 2

One-Hot State Assignment Alternative to minimum FF assignment If m states, use m flip-flops The current state is defined by the flip-flop that contains a 1 (all others MUST contain 0) i.e., one of the flip-flop outputs is hot (a 1 ) This method is also called one flip-flop per state Conceptually, the 1 is a token passed from the current state to the next state In reality, a FF s input logic will produce a 1 if and only if that FF is the next state One-Hot State Machine Design 3 3

Create Hardware From Diagram Does not require a state table! One flip-flop per state Create an AND gate per incoming transition and OR these together to make FF input logic One-Hot State Machine Design What are all the ways this can be the next state? Moore outputs: OR together outputs of FFs that represent states where the output is 1 Mealy: create an AND gate for each transition where the output is 1, and OR these together What are all the ways this output can be 1? 4 4

One-Hot Example: Ring Counter Each state gets a FF State vector is the output Y3 Y2 Y1 Y0 One-Hot State Machine Design 1 PRN D S0 PRN D S1 PRN D S2 PRN D S3 Q Q Q Q CLRN CLRN CLRN CLRN CLK RST 1 reset Four flip-flops S0 S1 S2 S3 Four states (0001, 0010, 0100, 1000) Reset into state 0001 (S0) 0001 0010 0100 1000 Output: Y3 Y2 Y1 Y0 5 5

One-Hot Reset State Remember, exactly one FF must contain a 1 at any moment Which state is the current state? The one that has a flip-flop with an output equal to 1 Which state is the next state? The one that has a flip-flop with an input equal to 1 One-Hot State Machine Design On a circuit reset, we need to load 1 into FF that represents the reset state, and 0 into the others Use PRESET (SET) ( on reset, become 1 ) for that FF Use CLEAR (RESET) ( on reset, become 0 ) for others 6 6

One-Hot Example: Ring Counter Each state gets a FF State vector is the output Y3 Y2 Y1 Y0 One-Hot State Machine Design 1 PRN D S0 PRN D S1 PRN D S2 PRN D S3 Q Q Q Q This FF represents the reset state S0 CLRN CLRN CLRN CLRN CLK RST 1 reset Four flip-flops S0 S1 S2 S3 Four states (0001, 0010, 0100, 1000) Reset into state 0001 (S0) 0001 0010 0100 1000 Output: Y3 Y2 Y1 Y0 7 7

One-Hot Terminology & Naming Since we use one flip-flop per state, we may use the words state and flip-flop interchangeably If we say the current state is S0, remember the current state is actually the complete state vector (all FF outputs, not just FF S0 s output) On the previous slide, the state vector for each state is that state s output (e.g., state S0 is actually state 0001) This means there are a lot of unused states! One-Hot State Machine Design For state S0 we created a flip-flop named S0 We might name its output S0 (same as the FF) or Q0 We might name its input D0, S0NEXT, etc. Its input and output cannot both be called S0 8 8

Design Tradeoffs Design Simplicity Usually less work to create, less work to debug, less work to add a new state because we handle each state separately Circuit Quality The design will require more flip-flops than a minimum flip-flop implementation May actually reduce combinational logic area If flip-flop input equations and circuit output equations are simpler as a result But this is not guaranteed! This means a one-hot design may or may not require more area/delay/power/energy One-Hot State Machine Design 9 9

Example One-Hot State Machine Pattern recognizer that detects the bit sequences 101 and 11 Overlapping sequences should be detected Design as a Moore machine Implement the state machine using one-hot encoding reset One-Hot State Machine Design 0 Nada 1 10 1 0 0 0 0 1 1 0 0 0 Input: A Output: Y 1 11 101 1 1 1 10 10

Example One-Hot State Machine Create a flip-flop for each state reset 0 One-Hot State Machine Design Nada 1 10 1 0 0 0 0 1 1 0 0 0 1 11 101 1 PRN D Nada PRN D S1 PRN D S10 Nada S1 S10 DNada Q D1 Q D10 Q 1 1 CLRN CLRN CLRN PRN D S11 PRN D S101 D11 Q S11 D101 Q S101 CLRN CLRN CLK 11 11

Example One-Hot State Machine Create a flip-flop for each state Implement reset Reset state Other states reset 0 One-Hot State Machine Design Nada 1 10 1 0 0 0 0 1 1 0 0 0 1 1 11 101 1 PRN PRN PRN PRN D Nada Nada Nada PRN D D PRN D D PRN D S1 S1 S1 PRN D D PRN D S10 S10 S10 Nada Nada Nada S1 S1 S1 S10 S10 S10 DNada DNada DNada Q Q Q D1 D1 D1 Q Q Q D10 D10 D10 Q Q Q 1 1 CLRN CLRN 1 1 CLRN CLRN CLRN CLRN CLRN CLRN CLRN 1 PRN D D PRN PRN D D PRN PRN D S11 S11 S11 PRN D S101 S101 S101 D11 D11 D11 Q Q Q S11 S11 S11 D101 D101 D101 Q Q Q S101 S101 S101 CLRN CLRN CLRN CLRN CLRN CLRN CLK CLK CLK RST RST 12 12

Example One-Hot State Machine Create FF input and circuit output equations DNada = Nada A + S10 A = (Nada + S10) A reset 0 One-Hot State Machine Design Nada 1 10 1 0 0 0 0 D1 = Nada A 1 1 0 0 0 D10 = S1 A + S11 A + S101 A = (S1 + S11 + S101) A Input: A Output: Y 1 11 101 1 1 1 D101 = S10 A Notice that the asynchronous reset is NOT an input to the DNada equation! D11 = S1 A + S11 A + S101 A = (S1 + S11 + S101) A The reset behavior is handled by the asynchronous clear/preset inputs Y = S11+ S101 Can use Boolean algebra to simplify 13 13

Example One-Hot State Machine The completed circuit . notA One-Hot State Machine Design 1 S10 PRN D Nada PRN D S1 PRN D S10 Q Q S1 Q S10 notA CLRN CLRN CLRN 1 reusing OR gate 1 S1 S11 S101 PRN D S11 PRN D S101 Q Q S11 S101 CLRN CLRN CLK OUT RST A 14 14

Mealy One-Hot reset 0/0 1/0 Nada 1 10 one of these has to be a 1 because it always has to be in some state One-Hot State Machine Design 0/0 Input: A Output: Y 0/0 1/1 1/1 DNada = Nada A + S10 A = (Nada + S10) A D1 = Nada A + S1 A + S10 A = (Nada + S1 + S10) A = A D10 = S1 A Y = S1 A + S10 A = (S1 + S10) A 15 15

Mealy One-Hot DNada = (Nada + S10) A D1 = A D10 = S1 A Y = (S1 + S10) A reset 0/0 1/0 Nada 1 10 One-Hot State Machine Design 0/0 Input: A Output: Y 0/0 1/1 1/1 A 1 PRN D Nada PRN D S1 PRN D S10 Q Q Q S10 S1 S10 CLRN 1 CLRN CLRN Y CLK RST 16 16

Optimizing One-Hot FSMs The logic equations from the direct translation may not be as simplified as they could be Optimization may not be critical; we already decided to use more flip-flops than the minimum Design simplicity is a major motivating factor! Some simplifications are straightforward, and can save time when drawing the schematic e.g., the factorization in the Moore example The downside is that changes may be less straightforward when debugging or modifying the FSM In this class, you do not have to simplify one-hot equations (it will be easier to debug!) One-Hot State Machine Design 17 17

ECE 352 Digital System Fundamentals One-Hot State Machine Design One-Hot State Machine Design 18 18