Optimizing Analog to Digital Conversion Techniques for Better Signal Integrity
Explore strategies for managing integration time variability and reducing noise in analog to digital conversion processes. Learn about the importance of differential signaling, crosstalk mitigation, and innovative circuit solutions to enhance signal accuracy and quality in electronic systems.
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Presentation Transcript
Analog to Digital Alice, triger Ernest Jamro
BNC (coaxial) vs twisted shielded better high frequency characteristic vs better noise suppression
Grounded Signal Sources Much better is differential signalling ( - signal should not be connected to the ground) Cut to eliminate noise Vg https://www.ni.com/pl-pl/support/documentation/supplemental/06/field-wiring-and-noise-considerations-for-analog-signals.html
Analog to digital converter How do you manage not known integration time (aperture time) which is about 20ns +/- 2ns. Aperture time noise (jiter) should be treated as the same kind of noise as signal noise - so noise (or uncurtainty) is +/- 10%!!! So why do you use 12-bit ADC (analog to digital converter) if aperture jiter is up to 10%? Same problem: crosstalk (parasitic cap.) between gate source and drain of the discharge transistor? Don't you want the aperture time to be 25ns, otherwise it is a dead 25ns- 20 ns = 5ns time? I suppose that the reason of this is that integrator discharge time must be 25 ns? ADC has 7 clocks cycles pipline latency, is it O.K.?
Solution A) discharge time must not overlap with the sample time (change only in CPLD) Integral[t2 - t0]= Integral[t1 - t0] + Integral[t2 - t1] so the integrator need not be fully discharged - just we need to know the initial value for the integrator - subtract samples to get the proper value - change only in CPLD
Solution B (requires significant changes) circuit similar to sigma-delta ADC - discharge the integrator with the known current (small change in the analog PCB board - replace transistor with a resistor?). In this case there is no discharge dead time - so sampling frequency can be doubled to 160 MS/s - employing integrators and sampling ADC one for rising another for falling clock edge.
