Optimizing FPGA Placement for Data Transmission Efficiency
Explore the best placement options for the FPGA in data transmission systems, comparing pros and cons of different configurations to maximize efficiency. Learn about data compression modes and the layout of SCD and PSD boxes for enhanced performance.
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Presentation Transcript
HERD-SCD Readout Electronic -20220502 Gongke,Qiaorui,Peng wenxi
Where to place the FPGA ? Plan A:FPGA on the TFH Pros Front-end fully digitalized No need for Fanout Board Cons: 1mW /Ch ~573W for the front-end 500W max totally one cable & Connector(~1.5m)/TFH 896 cables total
Where to place the FPGA Plan B:Add Front Fanout Board Pros 0.55mW/ch ~320W for the front-end one cable (~1.5m)/FBB (64 Cables total) Cons: Extra Front-end space needed
Data rate and data transmission data compression mode (data compression in the DAQ box): With trigger rate of 250 Hz. and data compression efficiency of 2% Total data rate 46Mbits/s Each data channel is about 11.4Mbits/s RAW data mode (no data compression outside of the CSS): With trigger rate of 250 Hz. Total data rate 2.3Gbits/s Each data channel is about 573Mbits/s Excluding Calo, the total bandwidth is 1 Excluding Calo, the total bandwidth is 1Gbits Gbits/s /s
Side SCD and PSD box layout PSD SCD
DAQ Box 4 DAQ boxes in 4 corners Size: ~25cm * 40cm * 8cm Data summary and compression DC/DC SCD&PSD DAQ
