Optimizing MIPS Pipelined Datapath Execution
Understand how to optimize the execution of MIPS assembly code on a pipelined datapath by incorporating stalls, forwarding paths, and branch prediction methods. Explore pipeline execution diagrams and clock cycle calculations for given code sequences.
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Presentation Transcript
Problem ??: (?? marks) Consider executing the following code on the MIPS pipelined datapath: add $t5, $t6, $t8 add $t9, $t5, $t4 lw $t3, 100($t9) sub $t2, $t3, $t4 Using the following diagram for the MIPS pipeline, draw the pipeline execution diagram and show the forwarding paths needed to execute the above code while incorporating any stalls or forwarding to resolve the dependencies. add $5, $6, $8 add $9, $5, $4 lw $3, 100($9) sub $2, $3, $4
Problem ??: (?? marks) Given the following code sequence: LW Label1: BEQ $t2, $t0, Label2 LW $t3, 0($t2) BEQ $t3, $t0, Label1 ADD $t1, $t3, $t1 Label2: SW $t1, 0(St2) $t2, 0($t1) # Not Taken once, then Taken # Taken Assume that this sequence is executed on a pipelined processor with a 5-stage MIPS pipeline using forwarding and a predict-taken branch prediction method. Draw the pipeline execution diagram for this sequence, assuming that branch instructions are resolved in the EX stage. How many clock cycles are needed to execute this sequence? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IF ID EX MEM WB LW $t2, 0($t1) IF ID **** EX MEM WB BEQ $t2,$t0, Label2(NT) IF ID EX MEM WB LW $t3, 0($t2) IF ID **** EX MEM WB BEQ $t3, $t0, Label1(T) IF **** ID EX MEM WB BEQ $t2, $t0, Label2(T) IF ID EX MEM WB SW $t1, 0(St2)
Problem ??: (?? marks) Given the following code sequence: LW Label1: BEQ $t2, $t0, Label2 LW $t3, 0($t2) BEQ $t3, $t0, Label1 ADD $t1, $t3, $t1 Label2: SW $t1, 0(St2) $t2, 0($t1) # Not Taken once, then Taken # Taken Assume that this sequence is executed on a pipelined processor with a 5-stage MIPS pipeline using forwarding and a predict-taken branch prediction method. Draw the pipeline execution diagram for this sequence, assuming that branch instructions are resolved in the EX stage. How many clock cycles are needed to execute this sequence? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IF ID EX MEM WB LW $t2, 0($t1) IF ID ID EX MEM WB BEQ $t2,$t0, Label2(NT) IF ID EX MEM WB LW $t3, 0($t2) IF ID ID EX MEM WB BEQ $t3, $t0, Label1(T) IF IF ID EX MEM WB BEQ $t2, $t0, Label2(T) IF ID EX MEM WB SW $t1, 0(St2)
Problem ??: (?? marks) Given the following code sequence: LW Label1: BEQ $t2, $t0, Label2 LW $t3, 0($t2) BEQ $t3, $t0, Label1 ADD $t1, $t3, $t1 Label2: SW $t1, 0(St2) $t2, 0($t1) # Not Taken once, then Taken # Taken Assume that this sequence is executed on a pipelined processor with a 5-stage MIPS pipeline using forwarding and a predict-taken branch prediction method. Draw the pipeline execution diagram for this sequence, assuming that branch instructions are resolved in the EX stage. How many clock cycles are needed to execute this sequence? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IF ID EX MEM WB LW $t2, 0($t1) IF ID ID ID EX MEM WB BEQ $t2,$t0, Label2(NT) IF ID EX MEM WB LW $t3, 0($t2) IF ID ID ID EX MEM WB BEQ $t3, $t0, Label1(T) IF IF IF ID EX MEM BEQ $t2, $t0, Label2(T) IF ID EX SW $t1, 0(St2)
