Optimizing Pipelining and Data Hazard Handling in Hardware

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Explore strategies for efficient pipelining and handling data hazards in hardware systems. Learn about pipeline stalls, register scoreboard tracking, stalling the pipeline, reducing data hazards through forwarding, eliminating data hazards via forwarding, and various forwarding conditions. Enhance your understanding of hardware optimization techniques through detailed explanations and visual illustrations.

  • Pipelining
  • Data Hazards
  • Hardware Optimization
  • Forwarding
  • Pipeline Stalls
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  1. Pipelining

  2. Handling Data Hazards in Hardware Stall the pipeline CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 sub $2, $1, $3 IM Reg DM Reg IM Reg DM Reg Bubble Bubble and $12, $2, $5 IM Reg DM Reg or $13, $6, $2 IM Reg DM add $14, $2, $2

  3. Pipeline Stalls To insure proper pipeline execution in light of register dependences, we must: Detect the hazard Stall the pipeline prevent the IF and ID stages from making progress insert no-ops into later stages

  4. Register Scoreboard Tracking Operand Availability Add valid bit to each register in the register file Valid (Full/Empty) Bit Hardware clears valid bit when an instruction that writes the register issues (leaves decode/register read stage) Register File Hardware sets valid bit when an instruction that writes the register completes Instructions not allowed to issue if any of their source registers are invalid

  5. Stalling the Pipeline Prevent the IF and ID stages from proceeding don t write the PC (PCWrite = 0) don t rewrite IF/ID register (IF/IDWrite = 0) Insert nops set all control signals propagating to EX/MEM/WB to zero

  6. Reducing Data Hazards Through Forwarding ALU add $2, $3, $4 IM Reg DM Reg ALU or $5, $3, $2 IM Reg DM Reg We could avoid stalling if we could get the ALU output from add to ALU input for the or ID/EX EX/MEM MEM/WB ALU 0 Registers Data Memory 1

  7. Eliminating Data Hazards via Forwarding CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 ALU IM Reg DM Reg sub $2, $1, $3 ALU IM Reg DM Reg and $6, $2, $5 ALU IM Reg DM Reg or $13, $6, $2 ALU IM Reg DM Reg add $14, $2, $2 ALU IM Reg DM sw $15, 100($2)

  8. Forwarding Paths 8

  9. Forwarding Conditions EX hazard if (EX/MEM.RegWrite and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 9

  10. Double Data Hazard Consider the sequence: add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 Both hazards occur Want to use the most recent Revise MEM hazard condition Only fwd if EX hazard condition isn t true 10

  11. Revised Forwarding Condition MEM hazard if (MEM/WB.RegWrite and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 11

  12. Does Forwarding Eliminate All Data Hazards CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 lw $2, 10($1) and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

  13. Does Forwarding Eliminate All Data Hazards CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 ALU IM Reg lw $2, 10($1) IM Reg and $12, $2, $5 IM or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

  14. Does Forwarding Eliminate All Data Hazards CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 ALU IM Reg DM lw $2, 10($1) IM Reg Bubble and $12, $2, $5 IM or $13, $6, $2 Bubble add $14, $2, $2 sw $15, 100($2)

  15. Does Forwarding Eliminate All Data Hazards CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 ALU IM Reg DM Reg lw $2, 10($1) ALU IM Reg DM Reg Bubble and $12, $2, $5 ALU IM Reg DM Reg or $13, $6, $2 Bubble ALU IM Reg DM add $14, $2, $2 ALU IM Reg sw $15, 100($2)

  16. Try this one... Show stalls and forwarding for this code add $3, $2, $1 lw $4, 100($3) and $6, $4, $3 sub $7, $6, $2

  17. Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall 13 cycles 11 cycles 5/28/2025 17

  18. Next Control hazards References for the current lecture Chapter 4.5, 4.6, 4.7, 4.8 5/28/2025 18

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