Personal Computer Architecture Components
Explore the intricate workings of personal computer architecture, from crystal oscillators to cache memory structures and chipset functionalities. Gain insights into core components like processors, memory controllers, and graphics adapters, delving into clock frequencies and cache hierarchies. Unravel the complexities of control units, memory buses, and various cache types, illustrating the interplay between hardware components in a computer system.
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Presentation Transcript
Crystal Oscillator Core Core Core Core L1 Cache L1 Cache L1 Cache L1 Cache L2 Cache L2 Cache L2 Cache L2 Cache Chipset DMI L3 Cache Graphics Controller Memory Controller Memory Bus PCI Express Graphics Adapter DRAM
E DRAM N S Hard Drive Controller W Memory Bus Control Unit Northbridge (Memory Controller) Southbridge (IO Controller) CPU Front Side Bus DMI ALU USB Registers PCI Express Network Adapter Graphics Adapter
Control Unit Control Unit Control Unit Control Unit Crystal Oscillator Core ALU Core ALU Core ALU Core ALU Reisters Registers Registers Registers L1 D Cache L1 D Cache L1 D Cache L1 D Cache L1 I Cache L1 I Cache L1 I Cache L1 I Cache L2 Cache L2 Cache L2 Cache L2 Cache Cache Memory Chipset DMI L3 Cache Graphics Controller Memory Controller Memory Bus PCI Express Graphics Adapter DRAM
Crystal Oscillator Base clock frequency = 100 MHz 1 cycle = 10 ns Voltage Time Voltage Time Voltage Time Voltage Time
CPU frequency = 3.5 GHz Crystal Oscillator Core Core Core Core Base clock frequency = 100 MHz L1 D Cache L1 D Cache L1 D Cache L1 D Cache L1 I Cache L1 I Cache L1 I Cache L1 I Cache L2 Cache L2 Cache L2 Cache L2 Cache Cache Memory Chipset DMI L3 Cache Graphics Controller Memory Controller Memory Bus PCI Express Memory bus frequency = 1.2 GHz Graphics Adapter DRAM
L1 D Cache L1 D Cache L1 D Cache L1 D Cache L1 I Cache L1 I Cache L1 I Cache L1 I Cache L2 Cache L2 Cache L2 Cache L2 Cache L3 Cache Dynamic Random Access Memory
Core Core Core Core L1 I Cache L1 D Cache L1 I Cache L1 D Cache L1 I Cache L1 D Cache L1 I Cache L1 D Cache L2 Cache L2 Cache L2 Cache L2 Cache DRAM Cache Memory Static Random Access Memory (SRAM) Dynamic Random Access Memory L3 Cache Graphics Controller Memory Controller Memory Bus
Core Core Core Core 64 KB (1 - 2 ns) L1 ICache L1 Cache L1 DCache L1 ICache L1 Cache L1 DCache L1 ICache L1 Cache L1 DCache L1 ICache L1 Cache L1 DCache 256 KB (3 4 ns) L2 Cache L2 Cache L2 Cache L2 Cache DRAM 8 GB (50 - 60 ns) 6 MB (10 15 ns) L3 Cache Graphics Controller Memory Controller Memory Bus
Core Core Core Core L1 ICache L1 DCache L1 ICache L1 DCache L1 ICache L1 DCache L1 ICache L1 DCache L2 Cache L2 Cache L2 Cache L2 Cache DRAM L3 Cache Graphics Controller Memory Controller Memory Bus Cache line 64 Bytes
Summary Central Processing Unit can have multiple cores Each core has a control unit, an Arithmetic and Logic Unit, and various registers Memory and graphics controllers are built into the CPU Base clock frequency is provided by a crystal oscillator Different components divide and multiply the base clock frequency as needed CPU can adjust its clock speed dynamically CPU cache is organised into three levels Data move between cache levels and DRAM in cache lines of 64 bytes
