Power-on Reset Cycle in PCF8575TI
When power is applied to VCC, the PCF8575TI device undergoes a power-on reset cycle, holding it in a reset condition until VCC reaches VPOR. This process involves specific timings for VCC transitions and glitch rejection to ensure proper initialization of the device. Learn more about the critical specifications and considerations for effective power-on reset operations.
Download Presentation
Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.
E N D
Presentation Transcript
Power on Reset PCF8575 TI
Power on Reset Cycle When power (from 0 V) is applied to VCC, an internal power-on reset holds the device in a reset condition until VCC has reached VPOR POWER-ON RESET CYCLE TOFF is the time that the VCC pin stays at 0 V VCC At that point, the reset condition is released and the device registers and I2C/SMBus state machine initialize to their default states After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle but there is no spec for ramp down/ramp up rates. TRISE is the time for the VCC pin to go from 0 V to original VCC value VPOR 0 V For best operation, TOFF > 100ms and TRISE < 10ms VPOR 1.65V typical TRISE TOFF Figure 1
POR Reset Glitch Rejection: Vcc VCC_GH VCC_GW Time Figure 2 Glitches in the power supply can affect the power-on reset performance of this device. The Glitch Width (VCC_GW) and Height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance and device impedance also are factors that affect power-on reset performance.
POR Reset Level VCC VPORR VPORF Time POR Time Figure 3 Another specification that is critical to the power-on reset operation is VPOR. This is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0.(VPORR =rise, VPORF=fall)
