Prefetching Championship Overview
Discover the 1st Instruction Prefetching Championship held in conjunction with ISCA 2020, focusing on microarchitecture competitions, simulation framework, evaluation methodology, and acknowledgments to the organizing committee. Learn about the submission process, acceptance rate, and the acceptance methodology based on paper reviews and simulator performance assessments.
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Presentation Transcript
1stInstruction Prefetching Championship May 31st, 2020 Held in conjunction with ISCA 2020 Seth Pugsley (Intel Labs) and Huiyang Zhou (NC State)
Welcome 1stInstruction Prefetching Championship History Many microarchitecture competitions over the years Motivation Front end critical to performance Code footprints growing
Simulation Framework ChampSim Started life as the simulator for DPC2 User replaceable prefetchers, cache replacement, and branch predictors Focuses on ease-of-use above accuracy or performance Core and cache parameters set to vaguely resemble an Intel Sunny Cove core, including 32KB L1-I cache 128KB to implement your best L1-I instruction prefetcher Prefetchers have access to both instruction cache accesses and branch patterns
Simulator Evaluation Methodology Public traces Combination of SPEC, client and server workloads Thanks again to Daniel Jim nez Secret traces Generated at Intel from client workloads Evaluation trace list Subset of public & secret traces where a perfect L1-I achieves >= +5.0% IPC 83 traces total Final score Geomean of all traces in the evaluation trace list with equal weight
Thanks to Organizing Committee Seth Pugsley (Intel Labs) Alaa Alameldeen (Intel Labs) Muawya Al-Otoom (Intel) Huiyang Zhou (NC State) Program Committee Mike Ferdman (Stony Brook University), Boris Grot (University of Edinburgh), Kei Hiraki (Preferred Networks), Daniel Jim nez (Texas A&M University), Hyesoon Kim (Georgia Tech), Anant Nori (Intel Labs), Arthur Perais (Microsoft), Joshua San Miguel (University of Wisconsin-Madison), Rami Sheikh (Microsoft), Chia-Lin Yang (National Taiwan University)
Submissions 4 page paper 1 prefetcher code file 8 papers accepted out of 16 submissions = 50% acceptance rate
Acceptance Methodology Paper reviews 4 reviews each Simulator performance + reviews used to accept papers 8 accepted papers include, with much overlap: Top 7 reviews Top 6 simulator performance Presentation order does not indicate competition performance
Workshop Program Papers and code will be available at the IPC-1 homepage: https://research.ece.ncsu.edu/ipc/ We will gladly publish updated code and/or papers if you provide them Talks have 20 minutes total including Q&A Schedule 4 papers Break 4 papers Concluding remarks and competition results
