Radiation-Hardened SONOS Embedded Non-Volatile Memory - AMICSA 2022 Details

RADIATION HARDENED BY DESIGN SONOS EMBEDDED NON-VOLATILE MEMORY IN 180NM Yaroslav Gubin AMICSA 2022

AMICSA 2022 PREREQUISITES The basic requirements are 42 to 64 portions of 256 words, 32 bits each. Out of the 32bits 8bits were used for ECC, the rest for bitstream. The eNVM Macro is an integral part of the FPGA for aerospace application and will be used as configuration memory. Third-party charge pump IP was initially chosen for HV generation, as it was designed specifically for programming and erasing the SONOS memory cells. HV stress per page is limited to 1000 HV OPs only, as the eNVM is going to be programmed in the lab before the mission and subblocks for HV generation will be disconnected from the power supply in the mission to avoid latch-ups. 2

AMICSA 2022 BIT CELL ARCHITECTURE Six-transistor bit cell flash architecture Direct and inverted data are stored and are used for differential sensing. Select Top and Select Bottom transistors are deployed. 3

AMICSA 2022 FLOATING GATE (FG) FLASH VS SONOS Advantages of SONOS cell: Much higher Endurance and Data Retention Lower programming and erase voltages Much lower HV OP current consumption Radiation Hardened by nature (no/tiny charge drainage, no moving bits) Disadvantages of SONOS cell: More complex control while programming and erasing (pulsing, POS HV slope), READ operation Longer HV OP Higher Danger of damage in HV Ops Process with 2 additional masks at least Higher effort on silicon validation (source: Cypress/Infineon) 4

AMICSA 2022 MEMORY CORE ORGANIZATION Word, bits Number of User Data Words Additional Configuration Space, Words 256 (56 active) Additional Redundancy Space, Words in Bank 0 and Bank 1 Page, Words Pages per Sector 32 256x64 256 8 (+2 flag bits) 32 32+1 (CONFIG/ REDUND) 2 8 8 Sectors per Memory Bank Memory banks ECC Bytes per Page ECC Bits per Word Total Amount of Memory, User Volume + CONFIG/REDUND, bits Sense amplifiers per Page 524288+16384 256 (+2 flag) 5

AMICSA 2022 CONFIG/REDUNDANCY SPACE 6:0 CONFIG space is written in RAID 1 like mirroring, same data in both BANKs 31:16 REDUNDANCY space is specific for each BANK 1. 2. 6

AMICSA 2022 DESIGN FOCUS HV OPs (operations) will be disabled during the mission User/Control Center will be able to reconfigure eNVM in the mission Therefore, key focuses were put on hardening of READ Operation eNVM INIT OP Test Modes Overall Safety and Integrity of the Data Mapping digital eNVM controller to the special libraries Sense Amplifier with 5 read modes multiple original algorithms of Data protection and recovery in the eNVM controller. In the full custom part architectural, design and layout measures were taken to reduce sensitivity against specified TID and SEE. 7

AMICSA 2022 SENSE AMPLIFIER To address degradation of programmed and erased thresholds of SONOS memory cells caused by aging in general and/or by collected dose, a special Sense Amplifier (SA) architecture was developed. 5 READ modes of the Sense Amplifier three differential and two pseudo single-ended modes with self-biasing and mismatch sampling. The user may configure the SAitself before the mission. SAcan be configured during the mission by overwriting eNVM controller registers. Self-calibration algorithm after every RESET sweeps operational modes of Sense Amplifiers, searching for suitable Bitline reference currents and VREAD voltage, changes trimming of the SAcontrol signals timings. 8

AMICSA 2022 ALGORITHMS OF DATA PROTECTION AND RECOVERY Whole page is buffered while READ into Data Out Shadow Buffer. The whole User Volume can be read out in a Burst READ. Error correction can be applied in a built-in scrubbing loop. To reduce sensitivity to the SET Data Path scrambling/descrambling is implemented along with internal Error Correction. RAID 1 type of storage is available for the user when enabled in eNVM CONFIG. AData Integrity Check feature in every WRITE. 9

AMICSA 2022 WRITE AND ERASE OPERATIONS WRITE Operations have optional WRITE VERIFY which is READ OP performed 1ms after WRITE is over. Additionally, the user may also enable automatic REDUNDANCYmapping. ERASE one PAGE is per hardcoded in the third-party CP IP internal FSM essentially just WRITE all zeroes. ERASE ALL to erase the entire User Volume and is just data shredding. 10

AMICSA 2022 DESIGN FOR MANUFACTURABILITY, DESIGN FOR YIELD AND TESTABILITY In order to make silicon validation easier and to pre-develop the production test program, be it wafer level or packaged chip level, 12 special Test Modes were developed, SCAN was added too and integrated into the digital eNVM controller. TYPE ADDR 0 1 2 3 4 5 6 7 8 TM TM00 TM01 TM02 TM03 TM04 TM05 TM06 TM07 TM08 TM NAME Virgin State to Normal Self-Calibration IDDQ RUN TM0+TM1 WL Leakage Test SA Test Cell Margin & BL Leakage Test Activate BL reference current, read out SA. For Cell Margin: set address, sweep VREAD, IBLREF Aux Charge Pumps Test Duty Cycle Measurement to track the auxiliary charge pump load, leakages Switch to EXTERNAL VREAD Reconfigures internal MUX to accept externally fed VREAD for Cell Margins measurements COMMENT FAIL CRITERIA N.A. NON-ERROR FREE READ >200uA, all sources See TM00 and TM01 >2uA leakage at RT NON-ERROR-FREE READ >2uA leakage at RT soft FAIL: >40%, hard FAIL: >90% See TM00 - TM08 Few HV Ops: WRITE FF, ERASE ALL, then WRITE code for self-cal. in CONFIG. Doesn't need USER inputs Algo looks up for error-free READ trim settings between two RESET sessions. Doesn't need USER inputs Measure VDD* current upon sequential analog block-by-block deactivation Wafer Level Test Inclusion (possible) Activate WL Leakage DAC/Comparator, as long as APSB is asserted, the test will run incrementally Running Modes of SA OP, DIFF to Single Ended, RAID 1. No ECC. ANALOG 9 10 11 12 13 TM09 TM10 TM11 TM12 DFT Special Registers Read Out REINIT from User source REINIT from CFG DI->SBI->SA->SBO->DO DFT ALL INTERNAL REGISTERS, such as Device ID and State Controller CONFIG RE-READ CONFIG cpace of eNVM into eNVM FSM registers 16 WORDs only (READ CONFIG PAGE 3 and 4 contents in the FSM registers), VOLATILE only Test for Data traverse: USER writes DI18_I, algo checks both DI & DO shadow buffers & SA Reserved N.A. N.A. DIGITAL FAILED FLAGS WRONG DATA TBD 11

AMICSA 2022 RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL SPECIFICATIONS Power Domains, V 1.8, 3.3 (+/-10%) Total Targeted Average Current Consumption in HV OP and READ, mA <50mA Total Targeted Average IDDQ Current Consumption, uA <10uA Operating Temperature, TA, oC -40 125 Storage Temperature, TA, oC -40 150 Data Retention, Years 10 Total Area, mm2 4.7 x 4.45 = 20.9 Targeted TID Tolerance, krad (Si) 100 Targeted SET Tolerance, LET, MeV*cm2/mg (Si) 60 12

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