RISC-V Assembly Examples and Translations
Dive into translating C if statements to RISC-V assembly with practical examples. Learn how to express conditions like greater than, less than, and equality using RISC-V branch instructions.
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Decisions in C and RISC-V CS3432 Fall 2024 Shirley Moore, Instructor svmoore@utep.edu September 19, 2024 1
Schedule for Todays Class Announcements CS Department Seminar this Friday, Sep. 20, 11am-12pm, CCSB 1.0410 David Mohaisen, Understanding the privacy dimension of wearables through machine learning-enabled inferences (See CS Dept Seminar webpage for Abstract) Quiz 2 due Friday, Sept. 20, by 11:59pm, not accepted late Homework 2 posted on Teams, first-come/first-served on presentation signup C decision constructs RISC-V branch instructions Translating C if statements to RISC-V assembly Unsigned comparisons Encoding RISC-V branch instructions Wide immediate values 2
C if statement if (condition) { // Statements to execute if condition is true } if (condition) { // Statements to execute if condition is true } else { // Statements to execute if condition is false } 3
C if statement examples if (x % 2) { printf( x is odd\n ); } if (x % 2) { printf( x is odd\n ); } else { printf( x is even\n ); } 4
RISC-V Branch Instructions Chapter 2 book slides 30, 35 beq, bne, blt, bge No bgt or ble how will we express these? Let s also look at these instructions on the RISC-V green card 5
Translating C if statements to RISC-V assembly Chapter 2 book slide 31 Let s practice with the following examples Example 1. Assume a is in x5, b is in x6, c is in x7 if (a > b) { c = a - b; } RISC-V translation bge x6, x5, L1 sub x7, x5, x6 L1: 6
C if statements to RISC-V assembly examples (cont.) RISC-V translation: Example 2. Assume a is in x28, b is in x29, c is in x30 if (a >= b) { c = a - b; } else { c = b - a; } blt x28, x29, else sub x30, x28, x29 beq x0, x0, next else: sub x30, x29, x28 next: 7
C if statements to RISC-V assembly examples (cont.) RISC-V translation: bge x29, x28, next bge x30, x29, next addi x31, x28, 0 next: Example 3. Assume a is in x28, b is in x29, c is in x30, d is in x31 if (a > b && b > c) { d = a; } Example 4. if (a < 0 || a > b) { c = -1; } RISC-V translation: blt x28, x0, doit bge x29, x28, next doit: addi x30, x0, -1 next: 8
Signed vs. Unsigned Comparison Book slide 36: 9
C unsigned comparison to RISC-V assembly Example 5. Same as Example 1 but with unsigned integers. unsigned int func(unsigned int a, unsigned int b) { unsigned int c = 0; if (a > b) { c = a - b; } return c; } Translate to RISC-V assembly code at godbolt.org with -O1 Compare with translation using signed integers. 10
Encoding Branch Instructions Chapter 2 book slide 38 (RISC-V translation of C code on slide 35) Try this example in the Venus RISC-V simulator. Let s practice by encoding the assembly code from Examples 1, 2, 4 Check your work using Venus. 11
Wide Immediates Assume a is in x5 a = 200001 What happens if you put the following instruction into Venus: addi x5, x0, 200001 Try using the li pseudo-instruction instead: li x5, 200001 Try the following immediate values: 2047, -2048, 2048, 4096, 4095, 6143 (=4096+2047), 6144, 8191, 8192, -4096, -2049 This is relevant to Lab 2, Task 5! 12
