RISC-V Operands and Memory Addressing CS3432 Fall 2024
Explore RISC-V operands and memory addressing techniques in CS3432 Fall 2024 with Shirley Moore. Learn about operator precedence, the Shunting Yard Algorithm, and translating C statements to RISC-V instructions.
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RISC-V Operands and Memory Addressing CS3432 Fall 2024 Shirley Moore, Instructor svmoore@utep.edu September 10, 2024 1
Schedule for Todays Class Announcements (5 min) Quiz 1 has been graded Lab 1 assigned on Teams, due Tuesday, Sept. 17, 11:59pm Will assign Quiz 2 and Chapter 2 homework next week Chapter 1 problem solution presentations (30 min) ASTs and Shunting Yard Algorithm (15 min) RISC-V operands and memory addressing (30 min) Chapter 2 book slides 6-12 Chapter 2 problems 2.1 (with registers), 2.3 2
Operator Precedence K&R Chapter 2, Table 2-1 (p. 53) Example (K&R p. 49): (x >> (p+1-n)) & ~(~0 << n) a) Translate by hand b) Build an expression tree, then traverse in postorder to generate 1) the postfix expression 2) the pseudo assembly language translation 3
Shunting Yard Algorithm https://mathcenter.oxford.emory.edu/site/cs171/shuntingYardAlgorithm/ https://en.wikipedia.org/wiki/Shunting_yard_algorithm We can extend the original algorithm to build an AST as follows: In addition to the operator stack, we use an additional stack of tree nodes. When the original algorithm would output an operand, we instead create a leaf node for it and push that onto the node stack. When the original algorithm would output an operator, we create a node for it and then pop the two top operands from the node stack (or one operand it the operator is a unary operator) and make them child nodes of the new node. We then push the new node onto the node stack. If the expression is well formed, we will be left at the end with one node on the node stack which is the root node of the AST. We will do this for Labs 1 and 2! Lab 1: Use the Shunting Yard algorithm to build the AST (This step is the frontend and is the same regardless of the target ISA). Lab 2: Traverse the AST in postorder to generate RISC-V assembly code. (This step is the backend and specific to the target ISA). 4
Chapter 2 problem 2.1 (with registers) 2.1 Translate the C statement below to RISC-V instructions, using pseudo-names for the operands and using as few RISC-V instructions as possible. Assume the C variables f, g, and h have already been placed in registers x5, x6, and x7, respectively. f = g + (h 5) addi x7, x7, -5 # x7 = h 5 add x5, x6, x7 # x5 = g + (h 5) 5
Chapter 2 problem 2.3 2.3 For the following C statement, write the corresponding RISC-V assembly code. Assume that the variables i and j are assigned to registers x28 and x29, respectively. Assume that the base addresses of the arrays A and B are in registers x10 and x11, respectively, and that A and B are arrays of 32-bit integers. B[8] = A[i-j]; sub x28, x28, x29 # x28 = i j slli x28, x28, 2 # x28 = 4*(i j) add x10, x10, x28 # x10 = &A[i j] lw x5, 0(x10) # x5 = A[i j] sw x5, 32(x11) # B[8]= A[i j] 6
