Schematic and Layout Checklist: TPS54J060/TPS54J061 BSR-MV HC

TPS54J060, TPS54J061 Schematic & Layout Checklist BSR-MV HC April 2021 1

Version History Version Number Version Number Release Date Release Date Comments Comments 1.0 April 7 2021 Initial Release 2

Agenda TPS54J060/1 Schematic Checklist TPS54J060/1 Layout Checklist Generic Best Practices for Schematics 3

TPS54J060, TPS54J061 Schematic Checklist BSR-MV HC April 2021 4

Schematic Notes: VIN Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 A minimum of 10 10- - F The input capacitors should give minimum ripple voltage desired for the application. Use WEBENCH or calculator to calculate the input capacitance. F input capacitance is required. required. Include a 10nF This capacitor minimizes high frequency voltage overshoots and undershoots from switching. 10nF- -100nF 0402 100nF 0402 input capacitor 5

Schematic Notes: BOOT Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Include a 0 0- - Optional but highly recommended in case of layout related issues. If the SW pin overshoot is too high, populating a 4.7 capacitor minimizes high frequency voltage overshoots on rising edge of SW pin resistor in series with the BOOT capacitor with an 0402 or larger 0402 or larger package size. 4.7- - resistor in series with the BOOT Connect at least 100 at least 100- -nF and 0402 size and 0402 size. 10-V rating, X5R or better dielectric, and 0402 size or larger ensure stable capacitance across all operating conditions nF capacitor from the BOOT pin to the SW pin, at least 10 at least 10- -V rated, X5R, V rated, X5R, 6 6

Schematic Notes: VCC Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Require at least 1 at least 1- - F, 6.3 VCC pin to PGND pins as the bypass capacitor. 1- F is the minimum capacitance required for stability of the internal regulator. 2.2 2.2- - F is recommended F is recommended. F, 6.3- -V V rating ceramic capacitor from An external bias with 3.3-V can be connected to this pin to save the power losses on the internal LDO 7

Schematic Notes: AGND Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Note which connections use AGND instead of PGND Ensure that separate symbols are used for AGND and PGND 8 8

Schematic Notes: PGND Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Ensure that PGND is common ground for output capacitors, input capacitors, and VCC capacitor Ensure that separate symbols are used for AGND and PGND 9

Schematic Notes: SW Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Connect this pin to the output inductor. Optional RC Snubber from SW to PGND (not shown here). These components can be not populated. Capacitor: typ 220 pF 220 pF with 0402 0402 package and 25V Resistor: typ near 6.8 6.8- - with minimum 0603 minimum 0603 package If the SW pin ringing is too high, a snubber helps minimize high frequency voltage overshoots and undershoots from switching 25V rating 10

Schematic Notes: FB (1/2) Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Ensure that the feedback divider network gives the appropriate Vout based on the Vref chosen. The FB pin must be connected to the AGND pin. Ensure that RFB_LS is between 0.499k and 20k between 0.499k and 20k. Less than 0.499K results in more current in FB path (less efficiency at light load) Greater than 20k can result in a design more susceptible to noise 11

Schematic Notes: FB (2/2) Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Determine if CFF is required for your application. In general, CFF is not needed for Vout <= 1.8 V. It is typically needed for Vout > 1.8V. CFF may result in a faster transient response, if needed. Ensure that RFF is substantially smaller than Rhs (R1 here): RFF should be between 100 Ohms and 1/10 of Rhs RFF makes the design less susceptible to load regulation issues. Using RFF between these values reduces its effect on the CFF-Rhs zero frequency. 12

Schematic Notes: TRIP Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Connect the resistor from the TRIP pin to the AGND pin. Use WEBENCH or calculator to calculate the RTRIP resistor value. Recommend 1% or better resistors 1% or better resistors for RTRIP . 13 13 13

Schematic Notes: SS/REFIN Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Connecting a capacitor from this pin to AGND Minimum soft-start time (1-1.5 ms) is fixed internally. A minimum 1 minimum 1- -nF nF capacitor is required. AGND pin programs soft-start time. 14

Schematic Notes: MODE Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 RMODE resistor sets FCCM/Skip-mode operation, as well as switching frequency TI highly highly recommends 1% resistor for improved accuracy Ensure that the proper RMODE resistor is chosen based on the table If shorting to AGND, use a 0-ohm resistor in the event of a design change. Note: MODE state set and latched at power-up 15 15 15 15

Schematic Notes: EN Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Floating this pin is not When using VIN or VDD to drive the EN pin, use a resistor divider and ensure that the voltage stays below 6V. not recommended. To start switching, this pin must be pulled high must be pulled high. The recommended max voltage rating to VIN unless the max VIN for your application is below 6V. max voltage rating on the EN pin is 6V 6V. Do not Do not connect EN pin directly 16

Schematic Notes: PGOOD Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Connect a 1k 1k- -100k PGOOD pin is an open-drain output so a pull-up is required when used 100k resistor to pull pull- -up up this pin. Recommend pulling up to VCC but not required. 17 17 17

Frequency Check Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Check fsw based on min on/off time and check that fsw is set correctly When exceeding fsw_max_ton, the fsw will decrease but the output will still be regulated. When exceeding fsw_max_toff, the output will become unregulated and UVP may trip. Ensure that the proper RMODE is selected for your application 18

Inductor/Capacitor Check Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 If input LC is used, check to make sure the Q is properly dampened (Not shown here) Use the recommended output inductance & capacitance in WEBENCH or calculator to meet design requirements The maximum Cout is a recommendation only. Exceeding this may be acceptable but the stability should be evaluated by measuring the load step response or bode plot. 19

Output Capacitor Check Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Check output cap meets stability, ripple and transient requirements. Check ESR of non ceramic caps. Check DC voltage derating of ceramic caps (50% to 70% typical) Ensure that the LC double pole is below 1/30th of switching frequency 20

Boot Capacitor & Snubber Check Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Check BOOT series RC Check SW node RC snubber values (Not shown here) 21

Power Sequencing Check Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Note the power sequencing and ensure that it is okay for your application 22

TPS54J060, TPS54J061 Layout Checklist BSR-MV HC April 2021 23

Layout Notes: VIN Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 A 0402 sized 0.01 0402 sized 0.01- - F to 0.1 capacitor must be placed as close as possible possible to the VIN and PGND pins to bypass high frequency noise and help reduce switch node ringing. It must be placed on the same side of the PCB as same side of the PCB as the IC. the IC. F to 0.1- - F F bypass as close as Larger VIN bypass capacitors should also be placed as close as possible to VIN and PGND pins behind this capacitor to minimize the input AC-current loop. 24

Layout Notes: BOOT Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Place the boot resistor (if used, not shown here) as close as possible close as possible to the BOOT pin, followed by the boot capacitor Use a 0.1uF to 1uF X5R (X7R for high- temperature applications) bootstrap capacitor with a 10V rating, as capacitor changes effective value based on DC voltage. Boot capacitor is used to generate gate drive voltage for high-side FET. A capacitor that is too small may not hold the gate drive voltage long enough. TI does NOT NOT recommend using vias on the BOOT path if there are concerns about EMI in your design. 25 25

Layout Notes: VCC Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Place the VCC bypass capacitor as close as possible as possible to the IC on the same side of the PCB the PCB. as close same side of If multiple capacitors are used, provide PGND PGND vias vias for each capacitor for each capacitor and ensure the return path is as short as possible. 26

Layout Notes: SW Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Ensure that the SW PCB trace is as short and wide as possible wide as possible to minimize PCB resistance and radiated noise. as short and If an RC snubber is used (not shown here), keep the snubber path short for low inductance and the best possible performance. Also, to minimize inductance, avoid using vias for the RC snubber routing and use very wide traces. To be most effective, the RC snubber should be connected between a large SW and PGND copper pour on the same side of the PCB as the IC. 27

Layout Notes: PGND Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Include as many as many vias thermal performance. vias as possible as possible for best Have a large solid ground large solid ground plane plane for GND. 28

Layout Notes: FB Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Place the feedback resistor near the device the device to minimize the FB trace distance. This is to minimize noise, as FB is a high-impedance node. near Connect the FB divider to the output voltage near the desired point of regulation. Avoid routing near noisy signals or power planes. 29

Layout Notes: TRIP Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Place the OCP setting resistor (RTRIP) as close to the device as possible. as close to the device as possible. Use AGND to connect RTRIP to GND. If TRIP ground is connected to a noisy ground, it may affect performance. Ensure that these traces are routed away from the switch node and other noisy signals. 30 30 30

Layout Notes: SS/REFIN Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Place the SS/REFIN capacitor CSS as close to the device as possible. close to the device as possible. as 31 31 31

Layout Notes: AGND Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Create a quiet AGND island for the return of noise sensitive pins Connect AGND to PGND at a single point point. For example, use vias to connect to an internal ground plane. a single 32

Layout Notes: EN Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Ensure that the EN pin is at maximum 6V. DO NOT connect EN pin to VIN DO NOT connect EN pin to VIN pin directly. pin directly. All routing for the EN pin should be placed away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling. 33

Layout Notes: PGOOD Rail #1 Rail #1 Rail #2 Rail #2 Rail #3 Rail #3 Keep the PGOOD resistor local to the device and place it as close as possible to the PGOOD pin (not shown here, on bottom layer). Ensure that the PGOOD resistor is kept away from fast switching voltage and current paths. 34 34 34

Generic Best Practices for Schematics BSR-MV April 2021 35

TPS54J060 SPECIFICATION INPUT VOLTAGE: 12V OUTPUT VOLTAGE: 1.8V OUTPUT LOAD CURRENT: 6A OUTPUT VOLTAGE RIPPLE: 10mVpp OUTPUT VOLTAGE UNDER/OVERSHOOT AFTER LOAD STEP: 50mV OUTPUT OVERCURRENT: 6.5A SOFT-START TIME: 1.5ms SWITCHING FREQUENCY: 1.1MHz OPERATING MODE: Skip-Mode OPERATING TEMPERATURE: 25 C Generic Best Practices for Schematics (1/5) Add text for expected currents and voltages near input and output terminals If pins are connected to off sheet supply, note the voltage level. Check standardized Info Note CGJ4J2X7R0J474K125AA Add text for significant off-page components (eg. output capacitors) No 4-way ties Different ground symbols for quiet and power ground Ground symbols should point down 36

TPS54J060 SPECIFICATION INPUT VOLTAGE: 12V OUTPUT VOLTAGE: 1.8V OUTPUT LOAD CURRENT: 6A OUTPUT VOLTAGE RIPPLE: 10mVpp OUTPUT VOLTAGE UNDER/OVERSHOOT AFTER LOAD STEP: 50mV OUTPUT OVERCURRENT: 6.5A SOFT-START TIME: 1.5ms SWITCHING FREQUENCY: 1.1MHz OPERATING MODE: Skip-Mode OPERATING TEMPERATURE: 25 C Generic Best Practices for Schematics (2/5) Check input cap meets bypass and ripple requirements Note part number or value, rdc and Irms, isat rating of inductor XEL4030-102MEB CGJ4J2X7R0J474K125AA Note part number or value, esr and voltage rating, dielectric for capacitors Check FB network is correct (including feedforward cap, external ripple injection and any external margining circuits) 37

Generic Best Practices for Schematics (3/5) Check other feature settings (adjustable current limit, adjustable ss, adjustable uvlo) Add Sync pin test point and Frequency Response Test Points Make sure all pins on a device are present on a device symbol Note NoPop and DNI components Note power sequencing 38

Generic Best Practices for Schematics (4/5) When optimizing size, use 0402 resistors with the L footprint. When designing for easy evaluation, use 0603 resistors for easy changing of components. Include test points for all pins and functionality you may need to test for the EVM Use X7R caps where feasible for BSR-MV products because of our extended operating temperature range where we might put the EVM in a temperature chamber. Depending on goals of EVM, anything between X7S or X5R may be acceptable. Generated .pdf are better than scanned .pdf for using Ctrl-F to find the devices and net in large schematics. 39

Generic Best Practices for Schematics (5/5) When optimizing size, use 0402 capacitors as much as possible. When designing for easy evaluation, use 0603 capacitors for easy changing of components. If cannot meet X7R or better in this package, then look at larger sizes. Have the test points towards the edge of the board, especially for DC signals Have the DC jumpers towards the edge of the board For options that are resistor selectable, have some or all options selectable using jumpers so that customers can experiment with them easily. 40

Important notice and disclaimer TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES AS IS AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. 41