Learn about the design of state machines and sequential machines, including Moore and Mealy models. Explore how synchronous and asynchronous circuits work, and understand the role of flip-flops in memory elements. Discover the differences between Moore and Mealy models in sequential circuits.
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Design of SequentialMachines The sequential logic circuits are consist of synchronous or clocked sequential circuits and an asynchronous logic circuits. In synchronous networks clocked flip- flops are used as memory elements, which change their individual states in synchronism with the periodic clock signal, the change in states of flip-flops and change in state of the entire circuit occurs at the transition of the clock signal. The synchronousor clocked sequential networks are represented by two models: Moore model: The output depends only on the present state of the flip-flops. Mealy model: The output depends on both the present state of the flip-flops and on the inputs. Moore Model As mentioned earlier, when the output of the sequential network depends only on the present state of the flip-flop, the sequential network is referred to as Moore model. Let us see one example of Moore model. Figure (1) shows a sequential network which consists of two JK flip-flops and AND gates. The network has one input X and one outputY. Fig. 1: Moore modelcircuit 34
In Figure (2) the inputs of the flip-flops is not used to determine the output-The output is derived using only present states of the flip-flops or combination of it. In general form the Moore model can be represented with its block schematic as shown in Figure 2 (a) and (b). Fig. 2: (a) Moore model without output decoder Fig. 2: (b) Moore circuit model with an output decoder In the Moore model, as output depends only on present state of flip-flops, it appears only after the clock pulse is applied, i.e. it varies in synchronism with the dock input. 35
Mealy Model When the output of the sequential network depends on both the present state of flip-flops and on the inputs, the sequential circuit is referred to as Mealy model. Figure (3) shows the sample Mealy model. In this type the output of the circuit is derived from the combination of present state of flip-flops and inputs of the circuit. Fig. 3: Mealy model Looking at Fig. 3, we can easily realize that, changes in the input within the clock pulses cannot affect the state of the flip-flop. However, they can affect the output of the circuit. Due to this, if the input variations are not synchronized with the clock, the derived output will also not be synchronized with the clock and we get false output (as it is a synchronous sequential network). The false outputs can be eliminated by allowing input to change only at the active transition of the clock (in our example HIGH-to-LOW). In general form the Mealy model can be represented with its block schematic as shown in Figure (4). Fig. 4: Mealy circuitmodel 36
