Sequential Logic Timing Analysis Concepts
Explore fundamental timing analysis concepts in sequential logic circuits, including setup time, hold time, aperture time, propagation delay, contamination delay, and dynamic discipline. Learn about the implications of these constraints on circuit design and how to determine the minimum clock period. Dive into the setup and hold time constraints for sequential circuits to ensure stable inputs and outputs.
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Presentation Transcript
COMP541 Sequential Logic Timing Montek Singh Feb 27, 2019 1
Topics Timing analysis flip-flops sequential systems clock skew 2
Input Timing Constraints Setup time: tsetup = time before the clock edge that data must be stable (i.e. not changing) CLK Hold time: thold = time after the clock edge that data must be stable D tsetup thold ta Aperture time: ta = time around clock edge that data must be stable (ta = tsetup + thold) 3
Output Timing Constraints Propagation delay: tpcq = max time after clock edge by which output Q is guaranteed to have stabilized (i.e., not changing anymore) Contamination delay: tccq = min time after clock edge during which Q will not have started changing yet CLK Q tccq tpcq 4
Dynamic Discipline The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge Specifically, the input must be stable at least tsetup before the clock edge at least until thold after the clock edge 5
Implications on Design Constrains operation Given a clock period, constrains circuit delays Given a circuit, constraints clock period The delay between registers (which impacts clock period) has a minimum and maximum delay, dependent on the delays of the circuit elements Delays of both comb. logic and flip-flops must be taken into account CLK CLK Q1 D2 CL R1 R2 (a) Tc CLK Q1 D2 (b) 6
Setup Time Constraint Setup time input to R2 must be stable at least tsetup before the clock edge constrains max delay from R1 through combinational logic What s min clock period? What s min period, Tc? Tc tpcq + tpd + tsetup tpd Tc (tpcq + tsetup) CLK CLK Q1 D2 CL R1 R2 Tc CLK So, clock period constrained by: Delay in CL Delay in previous reg (R1) Setup requirement in next reg (R2) Q1 D2 tpcq tpd tsetup 7
Hold Time Constraint Hold time input to R2 must be stable for at least thold after clock edge constrains the minimum delay from register R1 through the combinational logic often try to design circuits with 0 hold time requirement CLK CLK tccq + tcd thold tcd thold - tccq Q1 D2 CL R1 R2 CLK If there is no combinational logic between flipflops: thold tccq Q1 D2 tccq tcd thold 8
Timing Analysis Timing Characteristics CLK CLK tccq = 30 ps (FF contamination) tpcq = 50 ps (FF propagation) tsetup = 60 ps thold = 70 ps A B X' X C Y' Y D per gate tpd = 35 ps tcd = 25 ps tpd = tcd = Setup time constraint: Setup time constraint: tpd = 3 x 35 ps = 105 ps tcd = 25 ps Hold time constraint: tccq + tcd > thold ? (30 + 25) ps > 70 ps ? No! Tc fc = fc = 1/Tc = 4.65 GHz Tc (50 + 105 + 60) ps = 215 ps 9
Fixing Hold Time Violation Add buffers to the short paths: Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps CLK CLK A B X' X C Y' Y D per gate tpd = 35 ps tcd = 25 ps tpd = 3 x 35 ps = 105 ps tcd = 2 x 25 ps = 50 ps Setup time constraint: Hold time constraint: tccq + tpd > thold ? (30 + 50) ps > 70 ps ? Yes! Tc (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4.65 GHz 10
Hold Time Often flip-flops are designed for a hold time of zero To avoid these tricky problems 11
Clock Skew Clock doesn t arrive at all registers at the same time Skew is the difference between the arrival times of the clock edge at two different (typically neighboring) flip-flops Examine the worst case: guarantee that discipline is not violated for any register pair many registers in a system! delay CLK CLK1 CLK2 Q1 D2 CL R1 R2 tskew CLK1 CLK2 CLK 12
Setup Time Constraint with Clock Skew Worst case: CLK2 is earlier than CLK1 CLK1 CLK2 Q1 D2 CL R1 R2 Tc Tc tpcq + tpd + tsetup + tskew tpd Tc (tpcq + tsetup + tskew) CLK1 CLK2 Q1 D2 tpcq tpd tsetuptskew 13
Hold Time Constraint with Clock Skew Worst case: CLK1 is earlier than CLK2 tccq + tcd thold + tskew tcd thold - tccq + tskew If there is no combinational logic between flipflops: thold + tskew tccq Even if hold time is 0, only a very small skew is tolerated: tskew tccq 14
Reading, and next topic Reading: Section 3.5.1-3.5.3 Next topics: CPU datapath and control (Chapter 7.1-7.3) memories (Chapter 5.5) 15
