SLDO Design Overview and Progress Update
Design overview of a serial powering distribution solution for the EIC-LAS, emphasizing advantages over parallel configurations. Updates on current work progress, including completion stages and upcoming review. Various aspects such as bandgap, shunt regulator, and overcurrent protection are discussed with corresponding images provided.
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Presentation Transcript
Ancillary ASIC - SLDO design status ePIC Collaboration Jan 2025 Roy Wastie University of Oxford
Motivation for the SLDO A current based serial powering distribution solution for the EIC-LAS provides an acceptable material budget and power cable losses. Total supply current is defined by maximum current of a single module which is a significant advantage compared to the conventional parallel configuration where the supply current rises with increasing numbers of modules.
Design Overview TOP level excluding pads Pre-Regulator provides 1.5v to the BG and SLDO BG generates LDO variable reference OVP reference VOFS reference for voltage set across the SLDO for the required current. SLDO Pre-Regulator Bandgap SLDO
SLDO Shunt Reg Voltage across SLDO set by External R3 LDO
Overcurrent Protection Over-current protection Use more traditional LDO overcurrent protection Detect under-shunt condition Short pass transistor Effectively make output high impedance, and shunt behaves like an open circuit Some transient immunity Locks into overcurrent state until reset TMR protection Pull-ups for default operation Overcurrent Detection Register TMR PT Short Transient Protection Voltage buffer Defaults
Design Progress Current Work Schematic/simulations completed Design Review scheduled for January 30th with Michael Karagounis Layout underway SLDO Core complete (Iain Pre-reg Complete - awaiting latest version (Amanda) Bandgap underway (Roy) Top Level Schematic complete (Iain) Pads layout done (Iain) Post layout simulation still to do.
Design Progress Space for bandgap Biasing, USP, amplifiers etc etc 800um Pass Transistor Shunt Transistor 2500um METCT from top to bottom for high current supplies (Iin, VSS, VLDO). Already at maximum density
Design Progress Top Level Pad Ring Layout
Design submission How to submit? Original plan to send to BNL for March run However no DSA in place We're looking into ways of submitting from the UK
