SPARC
This content provides detailed information about SPARC, a project by Jean Soudier at IPHC in Strasbourg. It includes information on PADs count, FIFO floorplan, timing specifics such as clock period, duty cycle, and clock limitations. The content also features images showcasing the top view and floorplan of the project.
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Presentation Transcript
SPARC Jean Soudier IPHC - Strasbourg
PADs count Name Type Count (27) Name Type Count (24) PWELL Well 5 FIFO_Data Digital Output 3 DVDD Power 4 FIFO_Clk Digital Input 1 DVSS Ground 4 FIFO_Full Digital Output 1 AVDD Power 4 SC_Clk Digital Input 1 AVSS Ground 4 SC_SCK Digital Input 1 VCO_BIAS Power 1 SC_MISO Digital Output 1 ESD Protect 2 SC_MOSI Digital Input 1 SUB Substrat 1 SC_CSEL Digital Input 1 ANODE 1 TDC_Clk Digital Input 1 CATHODE 1 TDC_out Digital Output 1 RN Digital Input 1 MAT_RN Digital Input 1 AB_Clk Digital Input 1 PIX_BIAS Analog Input 9 19 f vrier 2025 Jean.soudier@iphc.cnrs.fr 2
Top view 19 f vrier 2025 Jean.soudier@iphc.cnrs.fr 3
FIFO floorplan Clk_pop Data_out[2:0] FIFO 750 m Clk_push RN Data_in[23:0] Push_af 160 m 19 f vrier 2025 Jean.soudier@iphc.cnrs.fr 4
Timing 1ns 1ns 40ps Between 2-4ns clock period 200ps uncertainty 200ps transition Duty cycle 60% UP / 40% DOWN Clk_pop 200MHz (limitation from PADs) -> 200/8 = 25 MHz (3 serializers) 19 f vrier 2025 Jean.soudier@iphc.cnrs.fr 5
