SRAM Arrays in Digital Systems
Explore the fundamentals of SRAM devices and arrays, including device characteristics, building memory systems, and increasing width and depth for efficient data storage. Dive into examples and key concepts to enhance your knowledge in digital system design.
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ECE 352 Digital System Fundamentals SRAM Arrays SRAM Arrays 1 1
SRAM Device Characteristics The device capacity is the total number of bits stored The width is number of bits stored at each location The depth is the number of locations that it contains Example: The 64k 8 device below has a capacity of 512 kbits SRAM Arrays indicates output is tristated if CS=0 64k x 8 RAM 8 input data address DIN ADR 16 8 DOUT output data chip select read/write CS R/W 2 2
Arrays of SRAM Devices Can build an m n SRAM memory system we need out of multiple, smaller SRAM devices Key ideas: Use multiple devices to create required memory capacity Distribute words (or parts of words) across several devices Need to be able to access all bits of the correct word at once SRAM Arrays 64k x 8 RAM 8 input data address DIN ADR 16 8 DOUT output data chip select read/write CS R/W 3 3
Increasing Width: 64k16 Array The available 64k 8 SRAM devices are deep enough, but they are not wide enough 64k x 16 SRAM Array 16 16 DI[15:0] DO[15:0] DI[15:0] DO[15:0] 16 A[15:0] A[15:0] 64k x 8 RAM SRAM Arrays 8 DI[15:8] A[15:0] DIN ADR 16 8 DO[15:8] DOUT CS CS R/W R/W Each SRAM device stores half of each word. 64k x 8 RAM 8 DI[7:0] A[15:0] DIN ADR 16 8 DO[7:0] DOUT CS CS R/W R/W CS CS R/W R/W 4 4
Increasing Depth: 128k8 Array The available 64k 8 SRAM devices are wide enough, but they are not deep enough 128k x 8 SRAM Array 8 8 DI[7:0] DO[7:0] DI[7:0] DO[7:0] 17 A[16:0] A[16:0] 64k x 8 RAM SRAM Arrays 8 DI[7:0] DIN ADR 16 A[15:0] 8 DO[7:0] DOUT CS1 CS R/W R/W addresses 0x10000-0x1FFFF DEC 1:2 A[16] CS CS1 CS0 0 EN 1 0 64k x 8 RAM 8 DI[7:0] DIN ADR 16 A[15:0] 8 DO[7:0] DOUT CS0 CS R/W R/W addresses 0x00000-0x0FFFF CS CS R/W R/W 5 5
Increasing Depth: 128k8 Array The available 64k 8 SRAM devices are wide enough, but they are not deep enough 128k x 8 SRAM Array 8 8 DI[7:0] DO[7:0] DI[7:0] DO[7:0] 17 A[16:0] A[16:0] 64k x 8 RAM SRAM Arrays 8 DI[7:0] DIN ADR 16 A[16:1] 8 DO[7:0] DOUT CS1 CS R/W R/W DEC 1:2 all odd addresses A[0] CS CS1 CS0 0 EN 1 0 64k x 8 RAM 8 DI[7:0] DIN ADR 16 A[16:1] 8 DO[7:0] DOUT CS0 CS R/W R/W CS CS all even addresses R/W R/W 6 6
Increasing Depth: 256k8 Array Array capacity now 2Mb, so requires 4 SRAM devices 256k x 8 SRAM Array 8 8 DI[7:0] DO[7:0] DI[7:0] DO[7:0] 64k x 8 RAM 8 DI[7:0] DIN ADR 18 16 A[17:0] A[17:0] A[15:0] 8 DO[7:0] DOUT addresses 0x30000-0x3FFFF CS3 CS SRAM Arrays R/W R/W 64k x 8 RAM 8 DI[7:0] DIN ADR 16 A[15:0] DEC 2:4 8 DO[7:0] DOUT addresses 0x20000-0x2FFFF A[17] A[16] CS3 CS2 1 3 2 1 0 CS2 CS 0 R/W R/W CS1 CS0 64k x 8 RAM CS EN 8 DI[7:0] DIN ADR 16 A[15:0] 8 DO[7:0] DOUT addresses 0x10000-0x1FFFF CS1 CS R/W R/W 64k x 8 RAM 8 DI[7:0] DIN ADR 16 A[15:0] CS CS 8 DO[7:0] DOUT addresses 0x00000-0x0FFFF CS0 CS R/W R/W R/W R/W 7 7
Array Design Example What if we needed to build a 128K 16 RAM out of 64K 8 RAMs? The total capacity of the array is 128k 16 = 2 Mbit Each 64K x 8 RAM has a capacity of 64k 8 = 512 kbit The array will require 2 Mbit / 512 kbit = 4 devices SRAM Arrays 8 8
Example: 128k16 Array 128k x 16 SRAM Array 16 16 DO[15:0] DI[15:0] DI[15:0] DO[15:0] 17 A[16:0] A[16:0] 64k x 16 64k x 8 RAM 64k x 8 RAM 8 8 DI[15:8] DI[7:0] DIN ADR DIN ADR 16 16 A[15:0] A[15:0] 8 8 DO[7:0] DOUT DO[15:8] DOUT SRAM Arrays CS1 CS1 R/W CS CS R/W R/W R/W 64k x 16 64k x 8 RAM 64k x 8 RAM 8 8 DI[15:8] DI[7:0] A[15:0] DIN ADR DIN ADR 16 16 A[15:0] 8 8 DO[15:8] DO[7:0] DOUT DOUT CS0 CS0 CS CS R/W R/W R/W R/W DEC 1:2 A[16] CS CS1 CS0 0 EN 1 0 CS CS R/W R/W 9 9
Example: 128k16 Array 128k x 16 SRAM Array 16 16 DO[15:0] DI[15:0] DI[15:0] DO[15:0] 17 A[16:0] A[16:0] 128k x 8 128k x 8 64k x 8 RAM 64k x 8 RAM 8 8 DI[15:8] DI[7:0] DIN ADR DIN ADR 16 16 A[15:0] A[15:0] 8 8 DOUT DO[7:0] DO[15:8] DOUT SRAM Arrays CS1 CS1 R/W CS CS R/W R/W R/W 64k x 8 RAM 64k x 8 RAM 8 8 DI[15:8] DI[7:0] A[15:0] DIN ADR DIN ADR 16 16 A[15:0] 8 8 DO[15:8] DOUT DO[7:0] DOUT CS0 CS CS0 CS R/W R/W R/W R/W DEC 1:2 A[16] CS CS1 CS0 0 EN 1 0 CS CS R/W R/W 10 10
SRAM Array Concepts The array capacity cannot be greater than the total capacity of the devices in the array Each bit of any array location is stored in one and only one physical location A read from any array address must return the data previously written to that address Writes must only affect the addressed location Each bit of the output data can only be driven by one device at any time None of array devices should be selected unless the array is selected SRAM Arrays 11 11
ECE 352 Digital System Fundamentals SRAM Arrays SRAM Arrays 12 12
