The Simplified Instructional Computer - Overview of SIC Machine
The Simplified Instructional Computer (SIC) consists of the standard model and the XE version, each with distinct features. The SIC Machine memory, registers, data formats, addressing modes, instructions, and I/O operations are detailed, providing insight into its functioning. Integers are stored as 24-bit binary numbers and characters using 8-bit ASCII codes. Addressing modes include direct and indexed, with specific target address calculations. The machine language instruction formats, arithmetic operations, conditional jumps, and I/O instructions highlight the SIC's capabilities and usage. Explore the components and operations of the SIC Machine for a comprehensive understanding of this simplified computer system.
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CHAPTER 2 THE SIMPLIFIED INSTRUCTIONAL COMPUTER
THE SIMPLIFIED INSTRUCTIONAL COMPUTER It has two versions: the standard model and the XE version. (XE = Extra Equipment or Extra Expensive )
THE SIC MACHINE Memory: Three consecutive bytes form a word (24 bits). There are a total of 32,768 (215) bytes in the computer memory. Registers There are 5 registers. Each register is 24 bits. Mnemonic Number 0 Use Accumulator; used for arithmetic Operations Index register; used for addressing Linkage register; the Jump to subroutine (JSUB) instruction stores the return address in this register. Program Counter Status word A X L 1 2 PC SW 8 9
THE SIC MACHINE Data Formats Integers are stored as 24 bit binary numbers 2 s complement representation is used for negative numbers Characters are stored using their 8 bit ASCII codes. There is no floating point hardware on the simple standard version. Machine Language Instruction formats All machine instructions have the following 24 bit format. 8 1 x 15 Opcode address The flag bit x is used to indicate the addressing mode.
THE SIC MACHINE Addressing Modes When x = 1 the addressing mode is indexed, when x = 0 it is direct. Mode Direct Indexed Indication x = 0 x = 1 Target address calculation TA = address TA = address + (X) (X) means contents of register X.
THE SIC MACHINE Instructions Instructions include LDA, LDX, STA, STX, ADD, SUB, MUL, DIV etc. All Arithmetic operations involve register A and a word in memory; the result is left in register A. An instruction COMP compares values in register A with a word in memory, it sets the condition code CC to indicate the result (<, = , or >). Conditional jump instructions are JLT, JEQ, JGT. JSUB stores the return address in register L and RSUB returns the program to a memory location whose address is contained in register L.
THE SIC MACHINE Input and Output This is performed by transferring one byte at a time to or from the rightmost 8 bits of register A. Each device is assigned a unique 8 bit code. There are three I/O instructions
I/O Instructions TD: (Test Device) It tests whether the addressed device is ready to send or receive a byte of data. The condition code is set to indicate the result of this test. < implies ready to send or receive; = implies the device is busy. RD: (Read data): Reads the data from a device when the device is ready. WD: (Write data) Writes data to a device. The sequence is repeated for each byte of data to be read or written.
THE SIC XE MACHINE Memory: The maximum memory is one megabyte (220 bytes). Registers All the registers for the simple machine plus the following: Mnemonic Number Use B 3 Base register, used for addressing S 4 General Working register T 5 General Working register F 6 Floating Point Accumulator.
THE SIC XE MACHINE Data Formats There is a 48 bit floating point data type with the following format. 1 11 S exponent 36 fraction The fraction is a value between 0 and 1. The offset is 1024 The sign of the floating point number is indicated by the value of s ( 0 = positive , 1 = negative.)
Instruction Formats Some instructions memory at all (formats 1 and 2) do not reference Two possible options are available for memory references; relative addressing (format 3) or using an extended address field to 20 bits (format 4) Bit e = 0 means format 3, e = 1 means format 4
Addressing Modes new relative provided by the extended version of format 3: Base relative addressing counter relative addressing. Two addressing modes are and program Mode Base relative Indication b= 1, p = 0 Target address calculation TA = (B) + disp (0 <= disp <= 4095) Program Counter b = 0, p = 1 TA = (PC) + disp (-2048 <= disp <= 2047)
Addressing Modes For base addressing disp is a 12 bit unsigned integer. For program counter relative addressing it is a 12 bit signed integer with negative values represented in 2 s complement. If bits b and p are set to 0, the disp field in format 3 is taken to be the target address.
Addressing Modes For format 4 bits b and p must be 0 and the target address is taken from the address field of the instruction. This is called direct addressing. Any of these addressing modes can also be combined with indexed addressing if bit x is set to 1. In such a case the contents of X, (X) is added in the target address calculation.
Addressing Modes Bits i and n are used to specify how the target address is used. If i = 1 and n = 0 the target address itself is used as the operand value. No memory reference is made. addressing. This is immediate If i = 0 and n = 1 the word at the location given by the target address is fetched. The value in this word is taken as the address of the operand value. addressing. This is indirect
Addressing Modes If bits i and n are both 0 or both = 1 the target address is taken as the location of the operand. This is referred to as simple addressing. Indexing cannot immediate or indirect addressing. be used with If bits n and i are both 0 then bits b, p and e are considered to be part of the address field of the instruction rather than flags indicating addressing modes.
Instruction Set Instruction Set All instructions in the standard version are still available. There are instructions to load and store the new registers (LDB, STB, etc) and to perform floating point arithmetic. (ADDF, SUBF, MULF, DIVF). Other instructions work on registers e.g. RMO, ADDR, SUBR, MULR, DIVR.
Directives Reserve the indicated number of words for a data area. Reserve the indicated number of bytes for a data area WORD Generate a one word integer constant BYTE Generate character or hexadecimal constant, occupying as many bytes as needed to represent the constant START Specifies the name and starting address for the program. END Indicates the end of the source program and optionally specify the first executable instruction in the program RESW RESB
INSTRUCTION SET TABLE Uppercase letters refer to specific registers. M indicates a memory address n indicates an integer between 1 and 16 r1 and r2 represent register identifiers. Parentheses contents of a register or memory location. are used to indicate the A (m..m+2) specifies that the contents of the memory location m through m+2 are loaded into register A
m..m+2 stored in the word that begins at address m. (A) contents of register A are P Privileged Instruction X Instruction available only on XE version F Floating point Instruction C Condition code CC set to indicate result of operation
SIC/XE INSTRUCTION SET Mnemonic ADD m ADDF ADDR r1, r2 AND m CLEAR r1 COMP m COMPF m COMPR r1, r2 DIV m DIVF DIVR r1, r2 Format 3/4 3/4 2 3/4 2 3/4 3/4 2 3/4 3/4 2 Code 18 58 90 40 B4 28 88 A0 24 64 9C Effect Notes A (A) + (m m+2) X, F X F (F) + (m m+5) r2 (r2) + (r1) A (A) & (m m+2) r1 0 X C X, F, C X, C (A) : (m m+2) (F) : (m m+5) (r1) : (r2) A (A) / (m m+2) F (F) / (m m+5) r2 (r2) / (r1) X
SIC/XE INSTRUCTION SET Mnemonic FIX FLOAT J m JEQ m JGT m Format 1 1 3/4 3/4 3/4 Code C4 C0 3C 30 34 Effect A (F) (Convert to Integer) X, F F (A)(Convert to float) PC m PC m if CC is set to = Notes X, F PC m if CC is set to > JLT m 3/4 38 PC m if CC is set to < L (PC) ; PC m JSUB m LDA m LDB m LDCH m LDF m 3/4 3/4 3/4 3/4 3/4 48 00 68 50 70 A (m m+2) X B (m m+2) A (rightmost byte) F (m m+5) m X, F
SIC/XE INSTRUCTION SET Mnemonic LDL m LDS m LDT m LDX m MUL m MULF m MULR r1, r2 LDA m NORM OR m RD m Format 3/4 3/4 3/4 3/4 3/4 3/4 2 3/4 1 3/4 3/4 Code 08 6C 74 04 20 20 98 00 C8 44 D8 Effect Notes L (m m+2) X X S (m m+2) T (m m+2) X (m m+2) A (A) * (m m+2) X,F A (A) * (m m+5) r2 (r2) * (r1) A (m m+2) F (F) (normalized) X, F X,F P A (A) | (m m+2) A (rightmost byte) Data
SIC/XE INSTRUCTION SET Mnemonic RMO r1 , r2 RSUB SHIFTL r1, n SHIFTR r1, n STA m STB m STCH m STF m STL m STS m STT m Format 2 3/4 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Code AC 4C A4 A8 0C 78 54 80 14 7C 84 Effect r2 (r1) PC (L) r1 (r1) left shift n bits X r1 (r1) right shift n bits X Notes X X m m+2 (A) X m m+2 (B) M (A) rightmost byte X, F m m+5 (F) m m+2 (L) X X m m+2 (S) m m+2 (T)
SIC/XE INSTRUCTION SET Mnemonic STX SUB m SUBF m SUBR r1, r2 TD m TIX m TIXR r1 WD m Format 2 2 Code 10 1C 5C 94 E0 2C B8 DC Effect Notes m m m+2 (X) A (A) (m m+2) F (F) (m m+5) r2 (r2) (r1) X, F X P, C C X, C X, F Test Device specified by (m) X (X)+1; (X) : (m..m+2) X (X)+1; (X) : (r1) Device specified by (m) (A) (rightmost byte)
EXAMPLES Sample data movement operations for the Simple SIC LDA STA LDCH STCH FIVE ALPHA CHARZ C1 ALPHA: FIVE: CHARZ: C1 RESW WORD BYTE RESB 1 5 C Z 1
EXAMPLES Same problem for the SIC/XE LDA STA LDCH STCH #5 ALPHA #90 (Load ASCII code for Z) C1 ALPHA: C1: RESW RESB 1 1
EXAMPLE 2 BETA = (ALPHA + INCR 1); DELTA = (GAMMA + INCR 1) LDA ADD SUB STA LDA ADD SUB STA ALPHA INCR ONE BETA GAMMA INCR ONE DELTA ONE: ALPHA: BETA: GAMMA: DELTA : INCR: WORD RESW RESW RESW RESW RESW 1 1 1 1 1 1
EXAMPLE 2 Same problem for the SIC/XE LDS LDA ADDR SUB STA LDA ADDR SUB STA INCR ALPHA S, A #1 BETA GAMMA S,A #1 DELTA ALPHA: BETA : GAMMA: DELTA : INCR : RESW RESW RESW RESW RESW 1 1 1 1 1
EXAMPLE 3 Sample looping and Indexing operations for Simple SIC The loop copies one 11 byte character string (STR1) to another string (STR2) LDX MOVECH: LDCH STCH TIX JLT ZERO STR1,X STR2,X ELEVEN MOVECH STR1: STR2: ZERO: ELEVEN: BYTE RESB WORD WORD C TEST STRING 11 0 11
EXAMPLE 3 Same problem for the SIC/XE LDT LDX MOVECH: LDCH STCH TIXR JLT #11 #0 STR1,X STR2,X T MOVECH STR1: STR2: BYTE RESB C TEST STRING 11
EXAMPLE 4 Looping and Indexing operations for SIC ALPHA, BETA and GAMMA are arrays of 100 words each. The corresponding elements BETA and stores the result in the elements of GAMMA. The value in the index register must be incremented by 3 for each iteration of the loop because each iteration processes a 3 byte (1 word) element of the array. loop of adds the ALPHA and
EXAMPLE 4 The Simple SIC Version LDA STA LDX LDA ADD STA LDA ADD STA COMP JLT ZERO INDEX INDEX ALPHA, X BETA, X GAMMA, X INDEX THREE INDEX K300 ADDLP ADDLP: INDEX: ALPHA: BETA GAMMA: ZERO : K300 THREE : RESW RESW RESW RESW WORD WORD WORD 1 100 100 100 0 300 3 : :
EXAMPLE 4 Same problem for the SIC/XE LDS LDT LDX LDA ADD STA ADDR COMPR JLT #3 #300 #0 ALPHA, X BETA, X GAMMA, X S, X X, T ADDLP ADDLP: ALPHA: BETA: GAMMA: RESW RESW RESW 100 100 100
Adding up 10 numbers in array MAK and storing the answer in memory location TOTAL LDS LDT LDX LDA AGAIN: ADDR ADD COMPR JLT STA #3 #30 #0 MAK, X S, X MAK, X X, T AGAIN TOTAL MAK: TOTAL: RESW RESW 10 1
Adding up numbers 0 to 100 and storing the answer in memory location SUM LDT LDX LDA AGAIN: ADDR TIXR JLT STA #100 #1 #0 X, A T AGAIN SUM SUM: RESW 1
EXAMPLE 5 The program reads 1 byte of data from device F1 and copies it onto device 05. INLOOP: TD JEQ RD STCH INDEV INLOOP INDEV DATA OUTLP: TD JEQ LDCH WD OUTDEV OUTLP DATA OUTDEV INDEV: OUTDEV: DATA: BYTE BYTE RESB X F1 X 05 1
EXAMPLE 6 Sample Subroutine call and record input operations for SIC The program reads a 100 byte record from an input device into memory. The read operation is placed in a subroutine which is called by the main program by using the JSUB instruction. At the end of the subroutine there is an RSUB instruction which returns control to the instruction that follows the JSUB. The READ subroutine also consists of a loop. Each execution of this loop reads one byte of data from the input device. The bytes that are read are stored in a 100 byte buffer area labeled RECORD.
EXAMPLE 6 JSUB READ READ: RLOOP: LDX TD JEQ RD STCH TIX JLT RSUB ZERO INDEV RLOOP INDEV RECORD,X K100 RLOOP INDEV: RECORD: ZERO: K100: BYTE RESB WORD WORD X F1 100 0 100
EXAMPLE 6 Same problem for the SIC/XE JSUB READ READ: LDX LDT TD JEQ RD STCH TIXR JLT RSUB #0 #100 INDEV RLOOP INDEV RECORD,X T RLOOP RLOOP: INDEV: RECORD: BYTE RESB X F1 100
