Transistors: A Brief Overview
Learn about transistors as switches, silicon as a semiconductor, MOS transistors, CMOS topologies, and the gate recipe in this informative overview by Montek Singh. Explore the basics of nMOS and pMOS transistors, the use of complementary networks, and how transistors function as voltage-controlled switches.
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Presentation Transcript
COMP541 Transistors and all that a brief overview Montek Singh Feb {7, 12}, 2018 1
Transistors as switches At an abstract level, transistors are merely switches 3-ported voltage-controlled switch n-type: conduct when control input is 1 p-type: conduct when control input is 0 g = 0 g = 1 d d d OFF nMOS g ON s s s s s s OFF g pMOS ON d d d 2
Silicon as a semiconductor Transistors are built from silicon Pure Si itself does not conduct well Impurities are added to make it conducting As provides free electrons n-type B provides free holes p-type Figure 1.26 Silicon lattice and dopant atoms
MOS Transistors MOS = Metal-oxide semiconductor 3 terminals gate: the voltage here controls whether current flows source and drain: are what the current flows between structurally, source and drain are the same Figure 1.29 nMOS and pMOS transistors
nMOS Transistors Gate = 0 OFF = disconnect no current flows between source & drain Gate = 1 ON= connect current can flow between source & drain positive gate voltage draws in electrons to form a channel Figure 1.30 nMOS transistor operation
nMOS and pMOS Transistors pMOS: Just the opposite Gate = 1 disconnect Gate = 0 connect Summary: g = 0 g = 1 d d d OFF nMOS g ON s s s s s s OFF g pMOS ON d d d 6
CMOS Topologies There is actually more to it than connect/disconnect nMOS: pass good 0 s, but bad 1 s so connect source to GND pMOS: pass good 1 s, but bad 0 s so connect source to VDD Typically use them in complementary fashion: nMOS network at bottom pulls output value down to 0 pMOS network at top pulls output value up to 1 only one of the two networks must conduct at a time! or output is undefined (or smoke may be produced!) if neither network conducts output will be floating pMOS pull-up network inputs output nMOS pull-down network 7
CMOS Gate Recipe Use complementary networks of p- and n-transistors called CMOS ( complementary metal-oxide semiconductor ) at any time: either pullup active, or pulldown active never both! VDD Use p-type here pMOS pull-up network pullup: make this connection when some combination of inputs is near 0 so that output = VDD inputs output nMOS pull-down network pulldown: make this connection when some combination of inputs is near VDD so that output = 0 (Gnd) Use n-type here Gnd
CMOS Inverter 0 1 Vout Valid 1 Vin Vout Invalid 1 0 Valid 0 Vin Only a narrow range of input voltages result in invalid output values. (This diagram is greatly exaggerated) A Y inverter
CMOS Complements A A conducts when A is high conducts when A is low A A B Series N connections: B Parallel P connections: conducts when A is high and B is high: A.B conducts when A is low or B is low: A+B = A.B A A B B Parallel N connections: Series P connections: conducts when A is high or B is high: A+B conducts when A is low and B is low: A.B = A+B
Inverter NOT VDD A Y P1 A Y Y = A N1 A 0 1 Y 1 0 GND P1 N1 A Y 0 ON OFF 1 1 OFF ON 0 11
NAND NAND A B Y P2 P1 Y Y = AB A N1 A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 B N2 A B P1 0 0 ON 0 1 ON 1 0 OFF 1 1 OFF P2 ON OFF ON OFF N1 OFF OFF ON ON N2 OFF ON OFF ON Y 1 1 1 0 12
3-input NOR A B C Y 15
2-input AND Gate? A B Y 16
A More Complex CMOS Gate Design a single gate that computes Y =(A+B) C Step 1. Determine pull-down network that sets output to 0 (A OR B) AND C Y=0 C A B Step 2. Determine pull-up network by walking through pulldown hierarchy, and replacing n-transistors with p-transistors series composition with parallel composition parallel composition with series composition A C B A B C Step 3. Combine the pull-up and pull-down networks together Y C A B
A More Complex CMOS Gate Single gate that computes called complex gate because it is not one of the basic gates (NAND, NOR, NOT, etc.) Y =(A+B) C A C this one is actually called OR-AND-INVERT (OAI) B Y C symbol: A B
One More Exercise Lets construct a gate to compute: F = A+BC = NOT(OR(A,AND(B,C))) Vdd A Step 1: Draw the pull-down network Step 2: The complementary pull-up network B C F A B this one is called AND-OR-INVERT (AOI) C
One More Exercise Lets construct a gate to compute: F = A+BC = NOT(OR(A,AND(B,C))) Vdd A Step 1: Draw the pull-down network Step 2: The complementary pull-up network Step 3: Combine and Verify B C F A B A B C F 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 C
Transmission Gates Transmission gate is a switch: nMOS pass 1 s poorly pMOS pass 0 s poorly Transmission gate is a better switch passes both 0 and 1 well When EN = 1, the switch is ON: A is connected to B When EN = 0, the switch is OFF: A is not connected to B En A B En En Symbol: A B En
Transmission Gate IMPORTANT: Transmission gates are not drivers will NOT remove input noise to produce clean(er) output simply connect A and B together current could even flow backward! use very carefully! immediately follow it up with a normal CMOS gate En A B En
Logic using Transmission Gates Typically combine two (or more) transmission gates Together form an actual logic gate whose output is always driven 0 or 1 Exactly one transmission gate drives the output; all remaining transmission gates float their outputs Example: XOR when C = 0, TG0 conducts F = A when C = 1, TG1 conducts F = A therefore: F = A xor C TG0 TG1 23
Tristate buffer and tristate inverter When enabled: sends input to output When disabled: output is floating ( Z ) Implementation: Tristate buffer using only a pass gate If on: output input If off: output is floating E Y A EN E 0 0 1 1 A 0 1 0 1 Y Z Z 0 1 A Y EN Tristate inverter Top half and bottom half are not fully complementary Either both conduct: output NOT(input) will act as a driver! Or both off: output is floating 24
Power Consumption Power = Energy consumed per unit time Dynamic power consumption Static power consumption
Dynamic Power Consumption Energy consumed due to switching activity: All wires and transistor gates have capacitance Energy required to charge a capacitance, C, to VDD is CVDD2 Circuit running at frequency f: transistors switch (from 1 to 0 or vice versa) at that frequency Capacitor is charged f/2 times per second assume 50% chance switching from 0 to 1 additional energy drawn from battery CVDD2 assume 50% chance switching from 1 to 0 no additional energy taken from battery stored energy is discharged Pdynamic = CVDD2f C is the total capacitance of circuit ( capacitive load ) VDD is the supply voltage f is the switching frequency
Static Power Consumption Power consumed when no gates are switching Caused by the quiescent supply current, IDD (also called the leakage current) Pstatic or Pleakage = IDDVDD VDD is the supply voltage IDD is the leakage current
Power Consumption Example Estimate the power consumption of a wireless handheld computer VDD = 1.2 V C = 20 nF f = 1 GHz IDD = 20 mA P = CVDD2f + IDDVDD = (20 nF)(1.2 V)2(1 GHz) + (20 mA)(1.2 V) = 14.4 W = 14.424 W + 24 mW
