Triangular Sorter: Memristor-Parallel Results

"Sorter, min-max cell, gate truth table, memristor modules, FPGA board details, power, timing, and comparison data for the Triangular Sorter project by Shri Kavya Alaparthy and Boddireddy Sindhu."

• Triangular Sorter
• Memristor-Parallel
• FPGA
• Circuit Design
• Technology

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Uploaded on Apr 20, 2025 | 0 Views

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Presentation Transcript

1. Triangular Sorter (Memristor-Parallel) SHRI KAVYA ALAPARTHY PSU ID:923357905 BODDIREDDY SINDHU PSU ID:951176634

2. Overview: Sorter Min-max cell Memristor FPGA Results

3. Sorter:

4. Min-Max Cell: Inputs are given in thermometric code. The drawback of this thermometric code is we need more number of bits per input.

5. Gate and its truth table:

6. Realization with two memristors:

7. Circuit when p=0:

8. Circuit when p not equal to 0:

9. Realization of OR gate:

10. AND gate space-time notation:

11. Memristor Module: Memristor module is written separately. Called twice for OR gate operation. Called thrice for AND gate operation.

12. Min Max Module: This is the module where memristor_module is called for the AND and OR operation. For OR gate, X = mem (mem (a, 0), B). For AND gate, X = mem(mem(mem (b,0),a),0)

13. FPGA Board: NEXYS 4 DDR Inputs: Slider switches Output: 7 segment display

14. Power:

15. Timing:

16. Comparision: Delay(ns) Area(mm2 ) Power Logic Net Total Memristor Setup 0.632 3.020 3.652 0.255 0.104 Hold 0.186 0.053 0.239 CMOS Setup 1.056 2.838 3.894 0.217 0.104 Hold 0.186 0.065 0.251

17. Results summary: Delay is decreased in memristor when compared to cmos. Area of the logic increased when memristor used compared to use of cmos. Static power is almost equal in both the cases. Dynamic power in memristor is bit high when compared to cmos.