Troubleshooting Overshoot and Undershoot in Switching Regulators
"Learn about the issue of overshot/undershot in switching regulators during power-up, its severity, potential fixes, root cause analysis, and effective workarounds to mitigate the problem. Find out how adding extra capacitance and optimizing configurations can reduce the impact on system functionality."
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PF8200 C0 ER030 SW5 OVERSHOOT ON LDO3 ENABLED JOAQUIN ROMO JULY, 2019 CONFIDENTIAL AND PROPRIETARY
Issue Description Customer Reported an over/under shoot on various switching regulators during the power up sequence. Overshoot on the Switching regulator occurs when the LDO is enabled after the Switching regulator. Glitch happen only with specific combination of SW regulator and LDOs, and it is consistent from part to part. When the Switching regulator is using the default output capacitance (2x 44uF) the overshoot/undershoot can be as high as +/-200mV Issue was first reported on B0 silicon at customer site and it has been confirm at NXP for both B0 and C1 silicon. 1 CONFIDENTIAL AND PROPRIETARY
Waveforms 2 CONFIDENTIAL AND PROPRIETARY
Severity Medium severity. The Magnitude of the overshoot/undershoot is big enough to violate the spec of SW5. this is critical for most of the systems. However, since the magnitude of the Overshoot can be reduced by adding extra capacitance on the SW5, and there are several configuration options to eliminate impact at system level, the issue can be rated as Medium severity. Potential Fixes: Not planned unless a major fix is needed. 3 CONFIDENTIAL AND PROPRIETARY
Root Cause The PF8200 uses a centralized Bias generation block and then, bias is routed to the respective blocks. Because of the high density routing on PF8200 some of these bias traces are too close to each other, causing an induced noise to the near by neighbors. On B0 silicon issue was observed as an interaction between two or more Switching regulators, therefore design team went ahead and provide shielding for all Bias traces for Switching regulator and LDOs. C1 silicon solves most of the issues observed on B0 silicon, however, we discovered that the bias trace for the OV/UV monitor of LDO3 which is side by side with the SW5 bias, is also affecting this regulator. When the LDO3 is enabled, the OV/UV monitor is enabled as well, causing the inductive kick on the SW5 bias line. (B0 silicon may experience interaction on other Switching regulators) 4 CONFIDENTIAL AND PROPRIETARY
Workarounds 1. The Overshoot/Undershoot is reduced with a higher output capacitance. Most of the system are already loading from 150uF to 200uF during integration with the i.MX processor. Based on the characterization test, the overshoot/undershoot, gets reduced to a total 50mV (peak to peak) with an output capacitance of 150uF. 5 CONFIDENTIAL AND PROPRIETARY
Workarounds 2. The Overshoot/Undershoot occurs only when the LDO is enabled, therefore it will occur only during the power up sequence and won t affect the normal operation of the system, unless the LDO is turn on and off dynamically. 3. If not all LDOs are used in the system, leave the LDO3 un-used to avoid any interaction with SW5. 4. If all LDOs are needed, try to assign LDO3 to a supply that is turned on before the SW5 and does not need to be turned on and off during the normal operation. 6 CONFIDENTIAL AND PROPRIETARY
