Troubleshooting VLSI Lab Assignments
Learn how to decipher errors, resolve common design problems, troubleshoot runtime issues, and more in VLSI lab assignments. Understand solutions for syntax errors, timing errors, license errors, and memory failures through practical examples and detailed explanations.
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Presentation Transcript
Debugging VLSI Lab Assignment Alok Lele
Deciphering Errors Accessing the log file: audio_single_rate.0<compilation_number> Search for ERROR TIPS: Run clean.sh the project before every compilation
Common Problems Design fails due to improper implementation Syntax errors Timing errors Solution Make sure you synthesize and run place & route in ISE Make sure that the filter design can operate above 100 MHz after the place and route Make sure the simulation output is correct
Common Problems Design fails in Place & Route when generating the .bit file Timing Error Solution: Try optimizing your current design Retiming Resource allocation
Common Problems License Errors: Re-compile the design after sometime.
Problems during runtime: Memory or cache failures: Incorrect handling of the system Solution: Disconnect all parts of the system and wait for a few minutes before retrying. Switch off the board during before disconnecting from the UART port (not required when disconnecting from the program port)
Problems during runtime Incorrect output: Incorrect handshake Incorrect state-machine Sub-optimal pipelining (Assignment 5) Solutions: Run multiple simulations on the test-bench Go through the simulation timing carefully
