VLSI SoC 2021 Singapore - Conference Overview
The VLSI SoC 2021 conference in Singapore, held from October 4-8, featured keynote speeches, industrial talks, and various tracks covering topics such as edge computing, data analytics, and security issues. The event included program chairs, general chairs, technical program committee (TPC) sub-tracks, statistics on submissions, accepted papers, and keynotes by distinguished speakers.
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Presentation Transcript
VLSI SoC 2021 Singapore, October 4 8 2021
The Conference General Chairs Anupam Chattopadhyay (NTU, SG) Andrea Calimera (Politecnico di Torino, IT) Program Chairs Chip Hong Chang (NTU, SG) Victor Grimblatt (Synopsys, CL) Conference topics Edge computing Acceleration of data-analytics Security issues
TPC 8 sub tracks Track 1: AMS, Sensors, and RF Track 2: VLSI Circuits and SoC Design Track 3: Embedded Systems Design & Software Track 4: CAD Tools and Methodologies for Digital IC Design & Optimization Track 5: Verification, Modeling and Prototyping Track 6: Design for Testability, Reliability and fault Tolerance - Track 7: Hardware Security Track 8: Emerging Technologies and New Computing Paradigms
Statistics Submissions: 75 58: main conference 8: Special Sessions 9: PhD Forum Accepted : 44 Main conference: 29 (19 for oral presentation, 10 for poster) PhD Forum: 8 Special Session: 7 Acceptance rate: 50%
Statistics by Track Track Submissions Accepted Acceptance rate PC members Analog, Mixed Signal, Sensors and RF 6 3 50% 15 CAD Tools and Methodologies for Digital IC Design & Optimization 5 3 60% 14 Design for Testability, Reliability and Fault Tolerance 6 5 83% 15 Embedded Systems Design & Software 5 3 60% 14 Emerging Technologies and New Computing Paradigms 14 7 50% 15 Hardware Security 5 2 40% 17 Verification, Modeling and Prototyping 7 2 29% 12 VLSI Circuits and SoC Design 10 4 40% 21
Number of Submissions by Country 18 16 15.4 14 13.2 12 Submissions 10 9 8 6.3 5.8 6 5 5 4 4 2 1.4 1.4 1.2 1 1 1 1 0.8 0.5 0.5 0.5 0.2 0.2 0.2 0.2 0 Country
Keynotes and Industrial Talks 3 keynotes The Deep Learning Software Stack: What Every NN Accelerator Architect Should Know, Kurt Keutzer, UC Berkeley, USA Preventing Secret leaks from Edge Devices, Ruby Lee, Princeton University, USA Efficient Neuromorphic Chips With Emerging Circuits and Technologies, Damien Querlioz, CNRS, Universit Paris-Saclay, France 3 Industrial talks Running Privacy-aware Machine Learning Applications on Edge Devices, Kaniskha Bhaduri, Apple, USA Sunil Cheruvu, Intelligent Edge security challenges and HW based technologies to the rescue, Intel, USA Optimizing memory device technology for energy efficient AI hardware, Peter Debacker, IMEC, Belgium
Special Sessions Special session 1: Secure hardware architectures Organizer: Nele Mentens, KU Leuven and University of Leiden Special session 2: Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures Organizers: Hussam Amrouch and Ilia Polian, University of Stuttgart, Germany Special session 3:Intelligent, Secure, Efficient Cyber-Physical Systems on Heterogeneous System on Chips Organizers: Apostolos P. Fournaris, Aris Lalos, Industrial Systems Institute, Research Centre ATHENA, PSP building, Platani, Greece.
