Athena DAQ Planning and Strategy
In the realm of Athena DAQ planning and strategy, components like Front End Boards, Front End Processors, Clock Distribution, and Front End Processors play crucial roles. These components work in harmony to ensure efficient data acquisition and processing, enabling synchronization, data compression, event finding, and more. Specialized solutions are tailored to meet specific requirements, such as clock jitter improvements for detectors needing higher precision. The discussion delves into interfaces, attainable specifications, and the intricate details of each component's function within the DAQ system.
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Presentation Transcript
Athena DAQ: Planning and Strategy
Components and Terminology: Front End Boards Front End Processors (on/near detector) (Electronics in DAQ room) Detector Front End Boards (on/near detector) DAQ Network / Tape (SDCC) Clock Distribution Computing (COTS) Detector Front End Boards (on/near detector) Detector (etc ) SDCC / DAQ/ Software Detector / DAQ DAQ Detectors DAQ
Clock Distribution: Consists of: Custom boards Optical links (e.g. lpGPT ecosystem) Function: distribute clock, synchronize detector timing with bunch structure, synchronize BX (and hence events) between detectors share other information between detectors bunch polarization prescaling Attainable specs: 100Mhz clock rate (variable within reasonable parameters due to beam energy) 1ps clock jitter Specialized solutions for detectors needing better clock jitter? Interfaces: EIC Front End Boards (FEB)
Front End Boards (FEB): Consists of: Specific to detector Integrated + boards near detector SiPM + FPGA &/or ASICS near / on detector ASICS on detector Function: ADC conversion Zero-suppression / other data compression Multiplex channels Assemble time frames Attainable Specs: Capable of streaming maximum luminosity in normal mode Not, in general, capable of streaming black events Need better definition than this! Interfaces: Clock Distribution DAQ computing &/or Front End Processors (FEP) eg lpGPT ecosystem, up to 20gbps Run mode configuration &/or slow controls
Front End Processors (FEP): Consists of: Custom Electronics in DAQ room FPGA based boards Function: Data Compression Event finding / selection Tradeoffs: Interesting Ideas FPGAs are well suited to Neural Nets / ML algorithms May be capable of very high performance But complex Custom electronics which becomes quickly obsolete Harder to program and adapt ML algorithms can be tricky to verify Likely need capability to run in passthrough mode Can be mimicked in CPUs We need a model for cost vs performance for FEP vs CPU based solutions to determine which detectors might benefit from or need FEP capabilities, and to determine whether they are a requirement or a luxury
FEB/FEP interface to DAQ: Consists of: Physical Level Fiber protocol (eg lpGPT ecosystem) Logical Level Headers to define data source, time frames, and data types? do we specify meaning of time frames? synchronize time frames? This interface needs to be well defined before any FEB/FEP electronics designs can be finalized
DAQ Network and Computing: Consists of: Commercial Off-the-shelf Hardware / Networks Function: Transport data Additional data compression Format data System control and configuration Track datafiles and configuration information Event Selection and tagging and accounting (HLT) QA Monitoring Logging Interfaces: FEB/FEP Software and Computing Events? Combine same time regions for all detectors in specific files? Time regions in multiple files split by detector?
DAQ Network and Computing: Other Related Components: Scalers Slow Controls Beam Parameters for analysis <-> feedback to collider from detectors
