FPGA Helix Tracking Algorithm for PANDA

This study introduces an FPGA-based helix tracking algorithm for the PANDA experiment's Straw Tube Tracker (STT). The algorithm involves road finding, momentum calculation, C++ performance study, VHDL implementation, and track quality assessment through circle parameter determination. Various images depict the STT structure, algorithm details, and performance evaluations based on realistic events with time-based information to improve momentum resolution.

• FPGA
• Helix Tracking
• PANDA Experiment
• Algorithm
• Performance Study

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1. FPGA Helix Tracking Algorithm for PANDA Yutie Liang, Martin Galuska, Thomas Ge ler, Wolfgang K hn, Jens S ren Lange, David M nchow, Bj rn Spruck, Milan Wagner II. Physikalisches Institut, JUSTUS-LIEBIG-UNIVERSIT T GIESSEN 09.09.2014

2. Outline 1. Introduction to the PANDA Straw Tube Tracker (STT) 2. Road finding and momentum calculation 3. Performance study with C++ 4. Implementation with VHDL 5. Summary and outlook 2

3. Straw Tube Tracker (STT) 4636 Straw tubes 23-27 planar layers 15-19 axial layers (green) in beam direction 4 stereo double-layers for 3D reconstruction, with 2.89 skew angle (blue/red) From STT : Wire position + drift time 3

4. Tracking Algorithm -- Road Finding Layer_ID Hit Hit Hit Hit Hit Hit Hit Hit Hit Hit Hit Tube_ID Hit: Seg_ID(3 bits) + LayerID(4 bits) + Tube_ID (6 bits) + Arrival time Boundary between two segments. 1: Start from inner layer Number of neighbor: 2: Attach neighbour hit to tracklet layer by layer 4 in axial layer; 6 in stereo layer 4

5. Tracking Algorithm -- helix parameters calculation Known : xi, yi, di Question: To determine a circle, y x2+ y2+ ax + by + c = 0 xc, yc, R Method: Minimize the equation E2= (xi2+ yi2+ a xi+ b yi+ c)2 (1/di)2 x S S S a S S Sx= xi Sxx= xixi Sxxx= xixixi xx xy x xxx xyy 1) Circle para. = S S S b S S xy yy y xxy S yyy S S N c S x y xx yy 2 2 2 + + + ( / ) 2 x ax y by r i 2 = i i i i / 1 n 2) Track quality. 2 d i 5

6. To Improve the Momentum Resolution -- using a 2nditeration y Pt(input) 1stiteration 2nditeration 0.2GeV/c : 0.195 0.0068 0.195 0.0068 0.5GeV/c : 0.5 0.0212 0.5 0.0164 1.0GeV/c : 0.99 0.0595 1.0 0.0317 2.0GeV/c : 1.85 0.213 2.0 0.073 xc, yc, R x 1stiteration 2nditeration Pt(GeV/c) 6 Pt(GeV/c)

7. Performance Study -- realistic events, time-based T0information: current event(Red) or other events(Green) Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) Event #4 Event #4 7

8. Assign Track to Correct Event T0information: current event(Red) or other events(Green) Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) Event #1 Event #1 8

9. Pz reconstruction 1: The radius, the position of the helix center in the XY plane are determined. 2: = kZ + 0 One cylinder the helix lies in. Based on Pt determined before y Crossing points (ellipse) One straw tube x z Track need to be tangent to the crossing ellipse. Gianluigi Boca and Panda Collaboration, Panda STT TDR, 2012 9

10. Pz reconstruction Method: Minimize E2= ( i+ kzi+ 0)2 (1/di)2 Known : zi, i, di Question: To determine a line, S k S S 1 z zz z = S S + kz + 0= 0 0 z 10

11. Pz reconstruction Pt = 0.5 GeV/c Pt = 1.0 GeV/c Pt = 2.0 GeV/c Pz(input) 0.25 GeV/c : 3.7 % 0.50 GeV/c : 4.0 % 1.00 GeV/c : 4.3 % Pz(input) 0.5 GeV/c : 3.1 % 1.0 GeV/c : 3.8 % 2.0 GeV/c : 4.2 % Pz(input) 1.0 GeV/c : 3.7 % 2.0 GeV/c : 4.8 % 4.0 GeV/c : 5.2 % 11

12. VHDL Implementation VHDL: Very-high-speed integrated circuits Hardware Description Language. Square root : Look-up table (1-2000) 1-4 4-16 16-64 64-256 Division: Look-up table a/b = (a*2^n) / (b*2^n) b*2^n in (0.5-1) 12

13. Performance at FPGA Pz calculation not finished yet. 1: Device Utilization Summary: Previous design 34% 1% 42% 1% 58% 96% 2: Time per event: For one event with 100 hits (6 tracks): (1) 100 clock cycles (cc) (2) 50 cc * 6 (3) ~200cc * 6 /(3 or 4) Previous: (1) 100 clock cycles (cc) (2) 50 cc * 6 (3) ~50cc * 6 13

14. Tracking at FPGA -- at low event rate Data flow: Hit information at PC FPGA, extract helix para. PC PC is used to draw hits and helix in the plot. The helix parameters come from FPGA.14

15. Tracking at FPGA -- at low event rate Data flow: Hit information at PC FPGA, extract helix para. PC PC is used to draw hits and helix in the plot. The helix parameters come from FPGA.15

16. Tracking at FPGA -- at low event rate Data flow: Hit information at PC FPGA, extract helix para. PC PC is used to draw hits and helix in the plot. The helix parameters come from FPGA.16

17. Tracking at FPGA -- 20 MHz Data flow: Hit information at PC FPGA, extract helix para. PC PC is used to draw hits and helix in the plot. The helix parameters come from FPGA.17

18. Tracking at FPGA -- 20 MHz Data flow: Hit information at PC FPGA, extract helix para. PC PC is used to draw hits and helix in the plot. The helix parameters come from FPGA.18

19. Tracking at FPGA -- 20 MHz Data flow: Hit information at PC FPGA, extract helix para. PC PC is used to draw hits and helix in the plot. The helix parameters come from FPGA.19

20. Summary and Outlook C++ VHDL Pt 1stiteration Pt2nditeration 2calculation Pz1stiteration On going Pz2nditeration On going 5 s/event , 100 FPGA @ 20MHz interaction rate Next to do: Optimize the VHDL code. Include MVD points Test with PTDAQ. 20

21. Thank you 21

24. VHDL implementation T0 T0 .. .. .. 9 Hit Hit Hit Hit Hit Hit Hit Hit Hit Hit Hit Hit 8 7 5 6 ToT 3 4 2 1 T0 Tracking module Input Interface Form tracklet 2D Mapping Calc Mom Index Ring Buffer 24

25. The Compute Node (CN) 25

26. Hardware Description Language VHDL, Verilog, SystemC VHDL: Very-high-speed integrated circuits Hardware Description Language. It s a dataflow language, unlike procedural computing languages such as C++ which runs sequentially, one instruction at a time. Signal A3_B1 ; Signal A4_B2 ; A1 A3 B1 B3 A3 <= A3_B1; B1 <= A3_B1; A B A4 B2 A2 B4 A4 <= A4_B2; B2 <= A4_B2; 26

27. Setup and Test PC as data source and receiver. Ethernet. Optical link (UDP by Grzegorz Korcyl ) (not integrated yet) Ethernet via Optical Link FPGA FIFO Tracking algorithm FIFO 27

28. Assign a track to the correct event T0information: current event(Red) or other events(Green) Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) Event #2 Event #2 28

29. Performance study single track y(cm) y(cm) 0.2GeV 0.5GeV x(cm) x(cm) 1GeV 2GeV y(cm) y(cm) x(cm) x(cm) 29

33. Pz reconstruction Pt = 0.5 GeV/c Pt = 1.0 GeV/c Pt = 2.0 GeV/c Pz(input) 0.25 GeV/c : 3.7 % 0.50 GeV/c : 4.0 % 1.00 GeV/c : 4.3 % Pz(input) 0.5 GeV/c : 3.1 % 1.0 GeV/c : 3.8 % 2.0 GeV/c : 4.2 % Pz(input) 1.0 GeV/c : 3.7 % 2.0 GeV/c : 4.8 % 4.0 GeV/c : 5.2 %