FPGA Programming Methods Overview by Dr.-Ing. Diana Ghringer

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Explore FPGA programming methods including hardware description languages (HDLs), model-based design, high-level synthesis tools (HLS), IP-cores, and more. Understand the comparison between VHDL and C/C++ for FPGA programming. Learn from the expertise of Dr.-Ing. Diana Ghringer at KIT University.

  • FPGA Programming
  • Hardware Description Languages
  • Model-based Design
  • High-Level Synthesis
  • IP-Cores
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  1. FPGA Programming Methods - An Overview Dr.-Ing. Diana G hringer, Dipl.-Ing. Matthias Birk Email: diana.goehringer@kit.edu ICAP ICAP KIT University of the State of Baden-Wuerttemberg and National Research Center of the Helmholtz Association www.kit.edu

  2. Outline Introduction and Motivation Programming Methods for FPGAs Hardware Description Languages (HDLs) Model-based Design (Matlab / Simulink) High-Level-Synthesis Tools (HLS) IP-cores Summary 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 2 Institute for Data Processing and Electronics

  3. Motivation Which is the best methodology to program my FPGA? Model-based Design HLS IP- HDL Library FPGA 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 3 Institute for Data Processing and Electronics

  4. Outline Introduction and Motivation Programming Methods for FPGAs Hardware Description Languages (HDLs) Model-based Design (Matlab/Simulink, Labview) High-Level-Synthesis Tools (HLS) IP-cores Summary 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 4 Institute for Data Processing and Electronics

  5. Hardware Description Languages Hardware Description Languages (HDLs) VHDL (Very High Speed Integrated Circuits Hardware Description Language) Since 1987 IEEE Standard Propagation: Mainly Europe Verilog Since 1995 IEEE Standard Propagation: Mainly USA 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 5 Institute for Data Processing and Electronics

  6. Hardware Description Languages Design Flow: VHDL versus C, C++ VHDL C++ Synthesis and Implementation Compiler .bit File .exe File 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 6 Institute for Data Processing and Electronics

  7. Hardware Description Languages: Comparison VHDL versus C, C++ C, C++ VHDL Sequential Instructions Hierarchical Behavioral descriptions Object Oriented Programming ( Structural descriptions ) Sequential Instructions Concurrent Instructions Hierarchical Behavioral descriptions Structural descriptions 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 7 Institute for Data Processing and Electronics

  8. Outline Introduction and Motivation Programming Methods for FPGAs Hardware Description Languages (HDLs) Model-based Design (Matlab/Simulink, Labview) High-Level-Synthesis Tools (HLS) IP-cores Summary 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 8 Institute for Data Processing and Electronics

  9. Model-based Design (Matlab/Simulink, Labview) Matlab HDL-Coder (evaluated in 2008) Generates readable VHDL-Code Only supports the basic Simulink-Toolbox / basic Matlab commands Xilinx SystemGenerator Own Code can be integrated as black box Cores generates with Vivado HLS can also be integrated Limited to the available toolboxes Generated Code is not readable 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 9 Institute for Data Processing and Electronics

  10. Model-based Design (Matlab/Simulink, Labview) Xilinx AccelDSP (evaluated in 2008, no longer available) Most powerful of these 3 Tools Generates HDL-Code from Matlab Generates von Simulink blocks Very expensive Generated VHDL-Code not readable Limitations for the Matlab Code 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 10 Institute for Data Processing and Electronics

  11. Outline Introduction and Motivation Programming Methods for FPGAs Hardware Description Languages (HDLs) Model-based Design (Matlab/Simulink, Labview) High-Level-Synthesis Tools (HLS) IP-cores Summary 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 11 Institute for Data Processing and Electronics

  12. High-Level Synthesis Tools: Motivation HDL C, C++ Abstraction level Development time Error Correction 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 12 Institute for Data Processing and Electronics

  13. High-Level Synthesis Tools: Overview A variety of open-source and commercial tools exist Very dynamic market: many changes and improvements in the past years High-Level language (C, C++, SystemC) VHDL, Verilog, Netlists Examples for commercial tools: Xilinx Vivado HLS (former Xilinx AutoESL) Calypto Catapult C (former Mentor Graphics Catapult C) ImpulseC Examples for open-source tools: ROCCC/ ROCCC 2.0 Trident LegUp 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 13 Institute for Data Processing and Electronics

  14. Hints for HLS Programming Restricted hardware resources: Select bitwidths of variables only as wide as necessary Store intermediate data only if necessary Don t use dynamic allocations or unbound loops Variety of different implementation strategies: Sequential implementation similar to C-Code is possible, but inefficient (Clock rate of the FPGA << Clock rate of a PC) Memory accesses, can be influenced using pragmas/directives Exploitation of Parallelism through: Loop-Unrolling (partial or complete) Pipelining Parallel implementation of independent functions Tradeoff: Hardware resources / power versus performance 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 14 Institute for Data Processing and Electronics

  15. High-Level Synthesis Tools ImpulseC Generates hardly readable HDL Code Better results compared to the Model-based design tools (Compared in 2008/2009) Fast generation of IP-Cores, especially hardware accelerators for Xilinx processors (generates the interface for the bus system) Supports pipelining and loop-unrolling Supports Xilinx and Altera FPGAs Only supports a subset of C (no C++ or SystemC) needs to be extended with special Pragmas C-Code needs to be modified to achieve a good result, e.g.: usage of exact bitlenghts for variables Costs Mostly a bit behind the standard Xilinx tools and FPGAs, as it is a third party tool 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 15 Institute for Data Processing and Electronics

  16. High-Level Synthesis Tools CatapultC (tested 2011) Supports C, C++ Generates hardly readable HDL Code Fast generation of IP-Cores Supports pipelining and loop-unrolling C-code is annotated via a user-friendly GUI, e.g. no modifications in the C-code needed for unrolling/pipelining loops or for organizing the memory layout Supports Xilinx and Altera FPGA C-Code needs to be slightly modified to achieve a good result, e.g.: usage of exact bitlenghts for variables No support for System C so far Costs More expensive than ImpulseC 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 16 Institute for Data Processing and Electronics

  17. High-Level Synthesis Tools Vivado HLS (formerly AutoESL) Supports C, C++ and SystemC Generates hardly readable HDL Code Fast generation of IP-Cores (incl. interfaces for the processors (Xilinx EDK tool), and for integration as a black box into Xilinx SystemGenerator) Supports pipelining and loop-unrolling C-code is annotated via a user-friendly GUI, e.g. no modifications in the C-code needed for unrolling/pipelining loops or for organizing the memory layout Low costs, comes with the Xilinx System Edition Tool set C-Code needs to be slightly modified to achieve a good result, e.g.: usage of exact bitlenghts for variables Costs 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 17 Institute for Data Processing and Electronics

  18. High-Level Synthesis Tools: Catapult C vs AutoESL vs IP-Core Results from the bachelor thesis of Thomas Kleiner AutoESL Catapult C IP-Core Throughput + ++ Efficiency (Area) + ++ Open-source programs are currently no alternative to commercial tools FIR FFT SAFT AutoESL + - ++ Catapult C ++ - + Optimal algorithm parameters for HLS Linear memory accesses Constant loop iterations 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 18 Institute for Data Processing and Electronics

  19. Outline Introduction and Motivation Programming Methods for FPGAs Hardware Description Languages (HDLs) Model-based Design (Matlab/Simulink, Labview) High-Level-Synthesis Tools (HLS) IP-cores Summary 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 19 Institute for Data Processing and Electronics

  20. IP-Cores Optimized cores in terms of performance and area Mostly only available as netlists / black box no source code available Costs 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 20 Institute for Data Processing and Electronics

  21. Outline Introduction and Motivation Programming Methods for FPGAs Hardware Description Languages (HDLs) Model-based Design (Matlab/Simulink, Labview) High-Level-Synthesis Tools (HLS) IP-cores Summary 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 21 Institute for Data Processing and Electronics

  22. Summary: FPGA Programming Methods Programming Method HDL: e.g. VHDL, Verilog, SystemVerilog Model-based Design: e.g. Matlab/Simulink Pros Cons Hardware skills necessary High development time Error-prone High Costs Less flexible Very flexible High abstraction level Library with standard components Rapid Prototyping High abstraction level Fast design space exploration Rapid Prototyping Only for IP-cores, not for a complete FPGA-Design Quality of results (ressources, performance) strongly depends on the C-code Costs High costs Source code often not available (only netlists) HLS Tools: e.g. Xilinx Vivado HLS, Calypto CatapultC, Impulse C Optimized modules IP-Cores 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 22 Institute for Data Processing and Electronics

  23. Summary: FPGA Programming Methods There is no single solution! Decision depends on Application requirements Background of the programmer Trend towards higher abstraction levels visible E.g. Xilinx Vivado HLS, Altera OpenCL Support New and better tools every year Goal to overcome the HDL programming hurdle for software / application programmers 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 23 Institute for Data Processing and Electronics

  24. THANK YOU! QUESTIONS? 03.06.2025 Dr.-Ing. Diana G hringer FPGA Programming Methods - An Overview 24 Institute for Data Processing and Electronics

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