Study of Electrothermal Imbalances in Parallel SiC MOSFETs
Alessandro Borghese, under the guidance of Prof. Andrea Irace, presents his research on electrothermal imbalances in parallel SiC MOSFETs. His work investigates the impact of uneven temperature rise, device mismatches, and unbalanced behavior on the reliability and lifetime of power converters. Through Monte Carlo simulations and case studies, guidelines for optimizing design and achieving reliable parallel connections are explored.
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Alessandro Borghese Tutor: Prof. Andrea Irace XXXIV Cycle - I year presentation Electrothermal Imbalances of Parallel SiC MOSFETs
Content My background Research activity Introduction Case study Results List of publications Next years I year credits- table for training Alessandro Borghese 2
My Background Alessandro Borghese received his BSc and MSc degrees in electronic engineering from the University of Naples Federico II. -Master thesis (Oct. 23rd, 2017) Efficiency Estimation and Comparison of Two Inverters for Electric Vehicles: Si vs. SiC Power Devices . Technical Centre of Toyota Motor Europe (Belgium). Nov. 2017 - Oct. 2018 Worked at Electrothermal Characterization Laboratory (DIETI, University of Naples Federico II). Oct. 2018, Public admission procedure 34thcycle ITEE PhD. Awarded w/ a ministerial scholarship tutor: Prof. Andrea Irace. My research activity is focused on power electronics and it specifically concerns the study of wide bandgap power semiconductor devices. Alessandro Borghese 3
Research Activity - Introduction SiC MOSFETs enable more efficient and compact converters thanks to excellent static and dynamic performances not available at high current levels (>200A) Great interest in multichip structures (parallel connection) LLOAD=50 H, ID 40A, VDC 420V Uneven temperature rise Device & circuit parameters mismatches Unbalanced devices behavior Shorter lifetime Derating rules & design optimization needed to reliably parallel SiC MOSFETs Monte Carlo simulations aimed at providing design guidelines for reliable paralleling Alessandro Borghese 4
Sources of current imbalance 700 VDS(M1) VDS(M2) ID(M1) ID(M2) Inductive turn-off of 2 parallel SiC MOSFETs 42.4 600 drain to source voltage [V] 34.5 500 drain current [A] 26.6 400 18.7 300 10.8 200 + - VPULSE 2.9 100 0 -5.0 15.0 15.2 LLOAD=50 H, ID 40A, VDC 420V time [ s] Static and transient unbalanced current sharing due to Mismatched -Device parameters: VTH, RON, CDS, CGD, CGS -Circuit parameters LS, Rgint, LG CGD CDS Rgint CGS LS Alessandro Borghese 5
Research Activity - Case Study Objective: estimate the temperature imbalance under realistic circuit operation 200 kHz 800 to 350 V 2 2 M1 5.33 0.59 M2 4.77 0.59 M3 4.21 0.55 M4 4.21 0.51 VTH[V] K [A/V2] 4 parallel MOSFETs per switching side. Each coupled w/ a Thermal Network (TN - from manufacturer): fully coupled ET simulations. Properly selected values of VTHand K. Circuit simulated over 0.2s of operation time (40 103 switching events). T(M3) 86 C vs T(M1) 41 C TMAX 45 C M3 has the highest switching power loss due to early turn-on and late turn-off. Alessandro Borghese 6
Research Activity - Results Objective: systematically relate dissipation non-uniformities of mismatched parallel devices to fabrication process rejection boundaries. 4 parallel MOSFETs under Double Pulse Test (DPT) Alessandro Borghese 7
Research Activity - Results Objective: systematically relate dissipation non-uniformities of mismatched parallel devices to fabrication process rejection boundaries. 7 sets of 1600 MC ET simulations by increasing the tolerance windows from 0.5 to from 3.5 4 parallel MOSFETs under Double Pulse Test (DPT) Alessandro Borghese 8
Research Activity - Results Objective: systematically relate dissipation non-uniformities of mismatched parallel devices to fabrication process rejection boundaries. 7 sets of 1600 MC ET simulations by increasing the tolerance windows from 0.5 to from 3.5 4 parallel MOSFETs under Double Pulse Test (DPT) At each switching instance Eoff(MOS#i) and Eon(MOS#i) are calculated and used to build the dissipated switching energy histograms. Alessandro Borghese 9
Research Activity - Results Objective: systematically relate dissipation non-uniformities of mismatched parallel devices to fabrication process rejection boundaries. 7 sets of 1600 MC ET simulations by increasing the tolerance windows from 0.5 to from 3.5 4 parallel MOSFETs under Double Pulse Test (DPT) At each switching instance Eoff(MOS#i) and Eon(MOS#i) are calculated and used to build the dissipated switching energy histograms. If TMAX=50 C gives a desired useful lifetime Always achievable at 50kHz and 100kHz only achievable at 200kHz if tolerance<1 Alessandro Borghese 10
Research Activity - Results Conclusion Statistical dispersions of VTH and RON for a commercial SiC power MOSFET were evaluated. Monte Carlo analyses of parallel SiC power MOSFET were performed to evaluate the energy/temperature unbalance. Example of design guidelines for thermal-aware design of multi-chip power module. Future Work Evaluate dependence on number of parallel devices. Alessandro Borghese 11
List of Publications A. Borghese et al., "Effect of Parameters Variability on the Performance of SiC MOSFET Modules," 2018 IEEE International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC), Nottingham, 2018, pp. 1-5. doi: 10.1109/ESARS-ITEC.2018.8607593 M. Riccio et al., "Experimental analysis of electro-thermal interaction in normally-off pGaN HEMT devices," 2018 IEEE International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC), Nottingham, 2018, pp. 1-6. doi: 10.1109/ESARS-ITEC.2018.8607347 A. Borghese et al., "Statistical Analysis of the Electrothermal Imbalances of Mismatched Parallel SiC Power MOSFETs," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 7, no. 3, pp. 1527-1538, Sept. 2019. doi: 10.1109/JESTPE.2019.2924735 A. Borghese et al., "An Experimentally Verified 3.3 kV SiC MOSFET Model Suitable for High-Current Modules Design," 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China, 2019, pp. 215-218. doi: 10.1109/ISPSD.2019.8757576 A. Borghese et al., An Efficient Simulation Methodology to Quantify the Impact of Parameter Fluctuations on the Electrothermal Behavior of Multichip SiC Power Modules, in Silicon Carbide and Related Materials 2018, 2019, vol. 963, pp. 855 858. M. Riccio et al., "Fully-Coupled Electrothermal Simulation of Wide-Area Reverse Conducting IGBTs," 2019 IEEE International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Lecco, 2019 A. Fayyaz et al., "Aging and failure mechanisms of SiC Power MOSFETs under repetitive shortcircuit pulses of different duration," 2019 International Conference on Silicon Carbide and Related Materials (ICSCRM), Kyoto, 2019 Alessandro Borghese 12
Next Years Credits year 1 Credits year 2 Credits year 3 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 Estimated 20 Estimated 10 Estimated Summary 22 5.9 39 66 Summary Summary bimonth 0.4 bimonth bimonth bimonth 11 4.8 bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth bimonth Check Total 22 30-70 5.9 10-30 39 80-140 66 5 5 Modules Seminars Research 0 0 0 0 0 0 0 0 0 0 1.1 8.9 10 5 6 9.6 10 5 0 5 10 10 35 60 45 61 60 60 10 16 10 0 0 0 0 0 0 0 0 0 0 0 0 180 Alessandro Borghese 13
