Vector Accelerator Array in Constrained Memory Bandwidth Project Proposal
Explore the innovative project proposal for an EDAN85 course led by teacher Flavius Gruian and student Arun Jeevaraj. The project involves a target application using a particle beam simulator in a linear model with high-density particle space. It focuses on maximizing DDR memory throughput while maintaining accuracy and fidelity in FPGA hardware design. The design flow includes simulation models in Matlab/Python for reference data, behavioral models in HLS/SystemC, FPGA implementation and verification using Vivado HLS.
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Presentation Transcript
Vector accelerator array in constrained memory bandwidth Project Proposal Course Code : EDAN85 Course Teacher : Flavius Gruian Student : Arun Jeevaraj
Target Application L distance Particle Beam simulator Linear Model with high density particle space: 10^6 particles Particles represented by space vector (dimension 6), x, y, z coordinates and momentum parameters 10^6 matrix multiplication per frame. Drift Space x1 x0 Drift space Application parameters Frame size : 45 MBytes for double precision Iterative Nature : Test for 1000 frames Drift space Drift space Drift space Drift space Frame Frame Frame Frame
Target Hardware Design. Target Design Design Requirements DDR MEMORY Maximise throughput Keep accuracy fidelity FPGA Hardware Design Vector Accelerator Array Vector Accelerator Array R A M R A M Use Memory Hierarchy Use Fixed Point Vector accelerator Array RAM
Design Flow Reference Simulation Model Matlab/Python Software Simulation Model for reference data (Matlab or python.) HLS/SystemC behavioral Models. Behaviour Simulation Model FPGA Implementation and verification. Vivado HLS Hardware Implementation Optional : Use ethernet I/O with PC for testing and verification.
