Clocking Options for ADC3664EVM via FMC Connector
"Learn how to provide sample clock and DCLKIN to the ADC3664EVM from an FPGA via the FMC connector. Ensure frequency coherence between the clocks and configure the EVM accordingly for optimal performance."
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Presentation Transcript
ADC3664EVM FMC clocking option 07/09/2021
Goal Provide sample clock and DCLKIN to the ADC3664EVM from FPGA via the FMC connector. NOTE: Please ensure that the Sample Clock and DCLKIN are frequency locked/coherent with one another (share the same reference). This should not be an issue if both PLLs in the FPGA are sharing the same input source.
ADC3664EVM FMC signals The sample clock input is single-ended, and comes from pin H4 of FMC. The DCLKIN input is differential, and comes from pins K16/K17 of FMC.
EVM configuration for FMC sample clock C21: Remove and use for R39. R39: Install 0.1 uF capacitor (use component C21). C26: Remove and use for R52. R52: Install 0.1 uF capacitor (use C26). R44 can be used if termination is required from FPGA signal.
EVM configuration for FMC DCLKIN R53: Remove and use for R50. R50: Install 0 ohm resistor (use component R53). Now LVDS Mux (U2) will pass DCLKIN_FPGA_P/N to DCLKIN_P/N.
