Verilog Algorithm State Machine Chart Supplement
Explore a supplement on implementing a bit counter in Verilog using algorithm state machine charts. Learn how to count the number of 1s in a binary sequence and store the count in Verilog. Dive into the ASM chart, datapath design, and Verilog module for this project.
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Supplement on Verilog for Algorithm State Machine Chart Based on Fundamentals of Digital Logic with Verilog Design and Fundamental of Logic Design Chung-Ho Chen 1
Problem: Bit Counter Count the number of 1s in A And store the number of 1s in B B = 0 ; while A 0 do if a 0= 1 then B = B + 1 ; end if; Right-shift A ; end while; 2
ASM Chart for Bit Counter Reset S1 Initialize B B 0 Load A S2 S1 Start another ? B = 0 ; while A 0 do if a 0= 1 then 0 0 1 s s s=1, start counting 1 B = B + 1 ; end if; Right-shift A ; end while; Load B Shift A Update B (a0=1) S2 S3 Shift right A Done 1 A = 0 ? B B + 1 Conditional output S2 which performs the shift is actually shifted at the next clock edge, so the checking of A, and a0 are performed before the shift of A. 0 0 a 0 1 3
Datapath for the bit counter If n = 8, need how many bits? A shift register A counter register Need to test if a0=1 Need test if A=0? Need load/enable signals +1 +1 A <> 0? 4
module bitcount (Clock, Resetn, LA, s, Data, B, Done); input Clock, Resetn, LA, s; input [7:0] Data; output reg [3:0] B; output reg Done; wire [7:0] A; wire z; reg [1:0] Y, y; reg EA, EB, LB; // control circuit parameter S1 = 2'b00, S2 = 2'b01, S3 = 2'b10; always @(s, y, z) begin: State_table case (y) S1: if (!s) Y = S1; else Y = S2; S2: if (z == 0) Y = S2; else Y = S3; S3: if (s) Y = S3; else Y = S1; default: Y = 2'bxx; endcase end always @(posedge Clock, negedge Resetn) begin: State_flipflops if (Resetn = = 0) y <= S1; else y <= Y; end continued in Part b. ASM Chart for Bit Counter to Verilog Code Reset S1 LB B 0 Load A Start another ? 0 0 1 y: PS Y: NS s s s=1, start counting 1 S2 S3 EA Shift right A Done 1 A = 0 ? B B + 1 Conditional output Z 0 EB 0 a 0 1 5
always @(y, A[0]) begin: FSM_outputs // Control data path // defaults EA = 0; LB = 0; EB = 0; Done = 0; case (y) S1: LB = 1; S2: begin ASM Chart for Bit Counter to Verilog Code Reset S1 EA = 1; if (A[0]) EB = 1; else EB = 0; Outputs in a state LB B 0 Load A Start another ? end Done = 1; 0 S3: 0 1 endcase s s end s=1, start counting 1 // datapath circuit S2 S3 // counter B always @(negedge Resetn, posedge Clock) if (!Resetn) B <= 0; else if (LB) B <= 0; else if (EB) B <= B + 1; EA Shift right A Done 1 A = 0 ? B B + 1 Conditional output Z 0 EB 0 shiftrne ShiftA(Data, LA, EA, 0, Clock, A); assign z = ~| A; // reduction NOR. a 0 1 endmodule 6
module shiftrne (R, L, E, w, Clock, Q); parameter n = 4; input [n-1:0] R; input L, E, w, Clock; output reg [n-1:0] Q; integer k; Shift Right Register always @(posedge Clock) begin if (L) Q <= R; else if (E) begin Q[n-1] <= w; for (k = n-2; k >= 0; k = k-1) Q[k] <= Q[k+1]; end end endmodule 7
